AESENC (XMM, XMM)

Experiment 1

Instruction: AESENC XMM0, XMM1

Code:

   0:	66 0f 38 dc c1       	aesenc xmm0,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 5.0
- Reference cycles: 3.13
- UOPS_EXECUTED.THREAD: 1.0

Experiment 2

Instruction: AESENC XMM0, XMM1
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	66 0f 38 dc c1       	aesenc xmm0,xmm1
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.0
- Reference cycles: 9.17
- UOPS_EXECUTED.THREAD: 10.0

Experiment 3

Instruction: AESENC XMM0, XMM1
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	66 0f 38 dc c1       	aesenc xmm0,xmm1
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.03
- Reference cycles: 9.17
- UOPS_EXECUTED.THREAD: 10.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: AESENC XMM0, XMM1

Code:

   0:	66 0f 38 dc c1       	aesenc xmm0,xmm1

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
AESENC XMM0, XMM1;
AESENC XMM1, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.5
- UOPS_EXECUTED.THREAD: 1.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: AESENC XMM0, XMM1
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	66 0f 38 dc c1       	aesenc xmm0,xmm1
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
AESENC XMM0, XMM1;
AESENC XMM1, XMM0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 13.0
- Reference cycles: 8.96
- UOPS_EXECUTED.THREAD: 10.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: AESENC XMM0, XMM1
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	66 0f 38 dc c1       	aesenc xmm0,xmm1
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
AESENC XMM0, XMM1;
AESENC XMM1, XMM0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.01
- Reference cycles: 9.17
- UOPS_EXECUTED.THREAD: 10.0

Experiment 7 (with the same register for different operands)

Instruction: AESENC XMM0, XMM0

Code:

   0:	66 0f 38 dc c0       	aesenc xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.98
- Reference cycles: 2.5
- UOPS_EXECUTED.THREAD: 1.0

Experiment 8 (with the same register for different operands)

Instruction: AESENC XMM0, XMM0
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	66 0f 38 dc c0       	aesenc xmm0,xmm0
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 13.02
- Reference cycles: 7.92
- UOPS_EXECUTED.THREAD: 10.0

Experiment 9 (with the same register for different operands)

Instruction: AESENC XMM0, XMM0
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	66 0f 38 dc c0       	aesenc xmm0,xmm0
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.02
- Reference cycles: 9.17
- UOPS_EXECUTED.THREAD: 10.01

Experiment 10 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Instruction: AESENC XMM0, XMM0

Code:

   0:	66 0f 38 dc c0       	aesenc xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
AESENC XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.98
- Reference cycles: 2.5
- UOPS_EXECUTED.THREAD: 1.01

Experiment 11 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Instruction: AESENC XMM0, XMM0
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	66 0f 38 dc c0       	aesenc xmm0,xmm0
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM0, XMM0;
AESENC XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 13.02
- Reference cycles: 8.13
- UOPS_EXECUTED.THREAD: 10.02

Experiment 12 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Instruction: AESENC XMM0, XMM0
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	66 0f 38 dc c0       	aesenc xmm0,xmm0
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
AESENC XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.02
- Reference cycles: 9.17
- UOPS_EXECUTED.THREAD: 10.0

Latency operand 2 → 1: 4

Experiment 1

Instruction: AESENC XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	66 0f 38 dc c8       	aesenc xmm1,xmm0
   5:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 13.02
- Reference cycles: 8.96
- UOPS_EXECUTED.THREAD: 10.0

Experiment 2

Instruction: AESENC XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	66 0f 38 dc c8       	aesenc xmm1,xmm0
   5:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.02
- Reference cycles: 9.17
- UOPS_EXECUTED.THREAD: 10.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: AESENC XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	66 0f 38 dc c8       	aesenc xmm1,xmm0
   5:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
AESENC XMM1, XMM0;
AESENC XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 13.02
- Reference cycles: 8.96
- UOPS_EXECUTED.THREAD: 10.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: AESENC XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	66 0f 38 dc c8       	aesenc xmm1,xmm0
   5:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
AESENC XMM1, XMM0;
AESENC XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.02
- Reference cycles: 9.17
- UOPS_EXECUTED.THREAD: 10.0

Experiment 5

Instruction: AESENC XMM1, XMM0
Chain instruction: AESENC XMM0, XMM1

Code:

   0:	66 0f 38 dc c8       	aesenc xmm1,xmm0
   5:	66 0f 38 dc c1       	aesenc xmm0,xmm1

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.02
- Reference cycles: 5.0
- UOPS_EXECUTED.THREAD: 2.0

Experiment 6 (with dependency-breaking instructions)

Instruction: AESENC XMM1, XMM0
Chain instructions: AESENC XMM0, XMM1;PXOR XMM1, XMM1

Code:

   0:	66 0f 38 dc c8       	aesenc xmm1,xmm0
   5:	66 0f 38 dc c1       	aesenc xmm0,xmm1
   a:	66 0f ef c9          	pxor   xmm1,xmm1

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 8.98
- Reference cycles: 6.67
- UOPS_EXECUTED.THREAD: 2.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: AESENC XMM1, XMM0
Chain instruction: AESENC XMM0, XMM1

Code:

   0:	66 0f 38 dc c8       	aesenc xmm1,xmm0
   5:	66 0f 38 dc c1       	aesenc xmm0,xmm1

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
AESENC XMM1, XMM0;
AESENC XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.0
- Reference cycles: 5.0
- UOPS_EXECUTED.THREAD: 2.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: AESENC XMM1, XMM0
Chain instructions: AESENC XMM0, XMM1;PXOR XMM1, XMM1

Code:

   0:	66 0f 38 dc c8       	aesenc xmm1,xmm0
   5:	66 0f 38 dc c1       	aesenc xmm0,xmm1
   a:	66 0f ef c9          	pxor   xmm1,xmm1

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
AESENC XMM1, XMM0;
AESENC XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 9.0
- Reference cycles: 5.21
- UOPS_EXECUTED.THREAD: 2.0

Experiment 9 (with the same register for different operands)

Instruction: AESENC XMM0, XMM0

Code:

   0:	66 0f 38 dc c0       	aesenc xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.5
- UOPS_EXECUTED.THREAD: 1.0

Experiment 10 (with the same register for different operands)

Instruction: AESENC XMM0, XMM0
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	66 0f 38 dc c0       	aesenc xmm0,xmm0
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 13.0
- Reference cycles: 8.13
- UOPS_EXECUTED.THREAD: 10.0

Experiment 11 (with the same register for different operands)

Instruction: AESENC XMM0, XMM0
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	66 0f 38 dc c0       	aesenc xmm0,xmm0
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
VZEROALL;
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.01
- Reference cycles: 9.17
- UOPS_EXECUTED.THREAD: 10.0

Experiment 12 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Instruction: AESENC XMM0, XMM0

Code:

   0:	66 0f 38 dc c0       	aesenc xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
AESENC XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.5
- UOPS_EXECUTED.THREAD: 1.0

Experiment 13 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Instruction: AESENC XMM0, XMM0
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	66 0f 38 dc c0       	aesenc xmm0,xmm0
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM0, XMM0;
AESENC XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 13.02
- Reference cycles: 9.38
- UOPS_EXECUTED.THREAD: 10.0

Experiment 14 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Instruction: AESENC XMM0, XMM0
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	66 0f 38 dc c0       	aesenc xmm0,xmm0
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
AESENC XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.01
- Reference cycles: 9.17
- UOPS_EXECUTED.THREAD: 10.0

AESENC (XMM, XMM) - Latency

Operands

Latency operand 1 → 1: 4

Latency operand 2 → 1: 4

Latency operand 1 → 1: 4

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Experiment 7 (with the same register for different operands)

Experiment 8 (with the same register for different operands)

Experiment 9 (with the same register for different operands)

Experiment 10 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 11 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 12 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Latency operand 2 → 1: 4

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 9 (with the same register for different operands)

Experiment 10 (with the same register for different operands)

Experiment 11 (with the same register for different operands)

Experiment 12 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 13 (source registers initialized by an instruction of the same kind, with the same register for different operands)

Experiment 14 (source registers initialized by an instruction of the same kind, with the same register for different operands)