MOV (M32, I32)

Experiment 1

Instruction: MOV dword ptr [R14], 16777216
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥7

Code:

   0:	41 c7 06 00 00 00 01 	mov    DWORD PTR [r14],0x1000000
   7:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 31 e6             	xor    r14,r12
  19:	4d 31 e6             	xor    r14,r12

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.96
- Reference cycles: 10.95
- UOPS_RETIRED.ANY: 8.0

Experiment 2 (with additional nop)

Instruction: MOV dword ptr [R14], 16777216
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥7

Code:

   0:	41 c7 06 00 00 00 01 	mov    DWORD PTR [r14],0x1000000
   7:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 31 e6             	xor    r14,r12
  19:	4d 31 e6             	xor    r14,r12
  1c:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.17
- Reference cycles: 11.16
- UOPS_RETIRED.ANY: 9.0

Experiment 1

Instruction: MOV dword ptr [R14+R13], 16777216
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥7

Code:

   0:	43 c7 04 2e 00 00 00 	mov    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 31 e5             	xor    r13,r12
  1b:	4d 31 e5             	xor    r13,r12

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.96
- Reference cycles: 10.95
- UOPS_RETIRED.ANY: 8.0

Experiment 2 (with additional nop)

Instruction: MOV dword ptr [R14+R13], 16777216
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥7

Code:

   0:	43 c7 04 2e 00 00 00 	mov    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 31 e5             	xor    r13,r12
  1b:	4d 31 e5             	xor    r13,r12
  1e:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 10.97
- Reference cycles: 10.94
- UOPS_RETIRED.ANY: 9.0

MOV (M32, I32) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤4

Latency operand 1 → 1 (address, index register): ≤4

Latency operand 1 → 1 (address, base register): ≤4

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤4

Experiment 1

Experiment 2 (with additional nop)