DIV (M64) - Latency


Operands


Latency operand 1 → 2 (address, base register): 73 ≤ lat ≤ 195

Latency operand 1 → 2 (address, index register): 195 ≤ lat ≤ 246

Latency operand 1 → 3 (address, base register): 246 ≤ lat ≤ 357

Latency operand 1 → 3 (address, index register): 73 ≤ lat ≤ 195

Latency operand 2 → 2: 70 ≤ lat ≤ 192

Latency operand 2 → 3: 70 ≤ lat ≤ 192

Latency operand 3 → 2: 70 ≤ lat ≤ 192

Latency operand 3 → 3: 70 ≤ lat ≤ 192


Latency operand 1 → 2 (address, base register): 73 ≤ lat ≤ 195

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 2 (address, index register): 195 ≤ lat ≤ 246

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, base register): 246 ≤ lat ≤ 357

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, index register): 73 ≤ lat ≤ 195

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 2: 70 ≤ lat ≤ 192

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 3: 70 ≤ lat ≤ 192

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 2: 70 ≤ lat ≤ 192

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 3: 70 ≤ lat ≤ 192

Experiment 1 (fast division)

Experiment 2 (slow division)