DIVPS (XMM, M128) - Latency


Operands


Latency operand 1 → 1: ≤65

Latency operand 2 → 1 (address, base register): ≤70

Latency operand 2 → 1 (address, index register): ≤70


Latency operand 1 → 1: ≤65

Experiment 1

Experiment 2

Experiment 3


Latency operand 2 → 1 (address, base register): ≤70

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6

Experiment 7

Experiment 8

Experiment 9

Experiment 10


Latency operand 2 → 1 (address, index register): ≤70

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6

Experiment 7

Experiment 8

Experiment 9

Experiment 10