BSR (R64, M64)

Experiment 1

Instruction: BSR R8, qword ptr [R14]

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 16.06
- Reference cycles: 16.05
- UOPS_RETIRED.ANY: 10.0

Experiment 2

Instruction: BSR R8, qword ptr [R14]
Chain instructions: MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 19

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 63 c0             	movsxd r8,r8d
   7:	4d 63 c0             	movsxd r8,r8d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d
  16:	4d 63 c0             	movsxd r8,r8d
  19:	4d 63 c0             	movsxd r8,r8d
  1c:	4d 63 c0             	movsxd r8,r8d
  1f:	4d 63 c0             	movsxd r8,r8d
  22:	4d 63 c0             	movsxd r8,r8d
  25:	4d 63 c0             	movsxd r8,r8d
  28:	4d 63 c0             	movsxd r8,r8d
  2b:	4d 63 c0             	movsxd r8,r8d
  2e:	4d 63 c0             	movsxd r8,r8d
  31:	4d 63 c0             	movsxd r8,r8d
  34:	4d 63 c0             	movsxd r8,r8d
  37:	4d 63 c0             	movsxd r8,r8d
  3a:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 20.0
- Core cycles: 36.0
- Reference cycles: 35.94
- UOPS_RETIRED.ANY: 29.0

Latency operand 1 → 3: 17

Experiment 1

Instruction: BSR R8, qword ptr [R14]
Chain instructions: CMOVZ R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 21

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 0f 44 ff          	cmove  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d
  1d:	4d 63 c0             	movsxd r8,r8d
  20:	4d 63 c0             	movsxd r8,r8d
  23:	4d 63 c0             	movsxd r8,r8d
  26:	4d 63 c0             	movsxd r8,r8d
  29:	4d 63 c0             	movsxd r8,r8d
  2c:	4d 63 c0             	movsxd r8,r8d
  2f:	4d 63 c0             	movsxd r8,r8d
  32:	4d 63 c0             	movsxd r8,r8d
  35:	4d 63 c0             	movsxd r8,r8d
  38:	4d 63 c0             	movsxd r8,r8d
  3b:	4d 63 c0             	movsxd r8,r8d
  3e:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 21.0
- Core cycles: 38.01
- Reference cycles: 38.01
- UOPS_RETIRED.ANY: 30.0

Latency operand 2 → 1 (address, base register): 20

Experiment 1

Instruction: BSR R8, qword ptr [R14]
Chain instructions: MOVSX R8, R8D;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8
Chain latency: 19

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 63 c0             	movsxd r8,r8d
   7:	4d 31 c6             	xor    r14,r8
   a:	4d 31 c6             	xor    r14,r8
   d:	4d 31 c6             	xor    r14,r8
  10:	4d 31 c6             	xor    r14,r8
  13:	4d 31 c6             	xor    r14,r8
  16:	4d 31 c6             	xor    r14,r8
  19:	4d 31 c6             	xor    r14,r8
  1c:	4d 31 c6             	xor    r14,r8
  1f:	4d 31 c6             	xor    r14,r8
  22:	4d 31 c6             	xor    r14,r8
  25:	4d 31 c6             	xor    r14,r8
  28:	4d 31 c6             	xor    r14,r8
  2b:	4d 31 c6             	xor    r14,r8
  2e:	4d 31 c6             	xor    r14,r8
  31:	4d 31 c6             	xor    r14,r8
  34:	4d 31 c6             	xor    r14,r8
  37:	4d 31 c6             	xor    r14,r8
  3a:	4d 31 c6             	xor    r14,r8

Show nanoBench command
Results:
- Instructions retired: 20.0
- Core cycles: 38.96
- Reference cycles: 38.96
- UOPS_RETIRED.ANY: 29.0

Latency operand 2 → 1 (address, index register): 20

Experiment 1

Instruction: BSR R8, qword ptr [R14+R13]
Chain instructions: MOVSX R8, R8D;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8
Chain latency: 19

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]
   5:	4d 63 c0             	movsxd r8,r8d
   8:	4d 31 c5             	xor    r13,r8
   b:	4d 31 c5             	xor    r13,r8
   e:	4d 31 c5             	xor    r13,r8
  11:	4d 31 c5             	xor    r13,r8
  14:	4d 31 c5             	xor    r13,r8
  17:	4d 31 c5             	xor    r13,r8
  1a:	4d 31 c5             	xor    r13,r8
  1d:	4d 31 c5             	xor    r13,r8
  20:	4d 31 c5             	xor    r13,r8
  23:	4d 31 c5             	xor    r13,r8
  26:	4d 31 c5             	xor    r13,r8
  29:	4d 31 c5             	xor    r13,r8
  2c:	4d 31 c5             	xor    r13,r8
  2f:	4d 31 c5             	xor    r13,r8
  32:	4d 31 c5             	xor    r13,r8
  35:	4d 31 c5             	xor    r13,r8
  38:	4d 31 c5             	xor    r13,r8
  3b:	4d 31 c5             	xor    r13,r8

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 20.0
- Core cycles: 39.0
- Reference cycles: 39.03
- UOPS_RETIRED.ANY: 29.0

Latency operand 2 → 1 (memory): ≤17

Experiment 1

Instruction: BSR R8, qword ptr [R14]
Chain instructions: MOVSX R12, R8D;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12
Chain latency: ≥19

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 63 e0             	movsxd r12,r8d
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	4d 63 e4             	movsxd r12,r12d
  28:	4d 63 e4             	movsxd r12,r12d
  2b:	4d 63 e4             	movsxd r12,r12d
  2e:	4d 63 e4             	movsxd r12,r12d
  31:	4d 63 e4             	movsxd r12,r12d
  34:	4d 63 e4             	movsxd r12,r12d
  37:	4d 63 e4             	movsxd r12,r12d
  3a:	4d 89 26             	mov    QWORD PTR [r14],r12

Show nanoBench command
Results:
- Instructions retired: 20.0
- Core cycles: 36.03
- Reference cycles: 36.03
- UOPS_RETIRED.ANY: 29.0

Latency operand 2 → 3 (address, base register): 20

Experiment 1

Instruction: BSR R8, qword ptr [R14]
Chain instruction: CMOVZ R14, R14
Chain latency: 2

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 0f 44 f6          	cmove  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 22.02
- Reference cycles: 21.99
- UOPS_RETIRED.ANY: 11.0

Latency operand 2 → 3 (address, index register): 20

Experiment 1

Instruction: BSR R8, qword ptr [R14+R13]
Chain instruction: CMOVZ R13, R13
Chain latency: 2

Code:

   0:	4f 0f bd 04 2e       	bsr    r8,QWORD PTR [r14+r13*1]
   5:	4d 0f 44 ed          	cmove  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 21.96
- Reference cycles: 21.96
- UOPS_RETIRED.ANY: 11.0

Latency operand 2 → 3 (memory): ≤17

Experiment 1

Instruction: BSR R8, qword ptr [R14]
Chain instructions: CMOVZ R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12
Chain latency: ≥21

Code:

   0:	4d 0f bd 06          	bsr    r8,QWORD PTR [r14]
   4:	4d 0f 44 e4          	cmove  r12,r12
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	4d 63 e4             	movsxd r12,r12d
  29:	4d 63 e4             	movsxd r12,r12d
  2c:	4d 63 e4             	movsxd r12,r12d
  2f:	4d 63 e4             	movsxd r12,r12d
  32:	4d 63 e4             	movsxd r12,r12d
  35:	4d 63 e4             	movsxd r12,r12d
  38:	4d 63 e4             	movsxd r12,r12d
  3b:	4d 63 e4             	movsxd r12,r12d
  3e:	4d 89 26             	mov    QWORD PTR [r14],r12

Show nanoBench command
Results:
- Instructions retired: 21.0
- Core cycles: 37.99
- Reference cycles: 37.97
- UOPS_RETIRED.ANY: 30.0

BSR (R64, M64) - Latency

Operands

Latency operand 1 → 1: 16

Latency operand 1 → 3: 17

Latency operand 2 → 1 (address, base register): 20

Latency operand 2 → 1 (address, index register): 20

Latency operand 2 → 1 (memory): ≤17

Latency operand 2 → 3 (address, base register): 20

Latency operand 2 → 3 (address, index register): 20

Latency operand 2 → 3 (memory): ≤17

Latency operand 1 → 1: 16

Experiment 1

Experiment 2

Latency operand 1 → 3: 17

Experiment 1

Latency operand 2 → 1 (address, base register): 20

Experiment 1

Latency operand 2 → 1 (address, index register): 20

Experiment 1

Latency operand 2 → 1 (memory): ≤17

Experiment 1

Latency operand 2 → 3 (address, base register): 20

Experiment 1

Latency operand 2 → 3 (address, index register): 20

Experiment 1

Latency operand 2 → 3 (memory): ≤17

Experiment 1