ADD (M32, I32)

Experiment 1

Instruction: ADD dword ptr [R14], 16777216
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥7

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 31 e6             	xor    r14,r12
  19:	4d 31 e6             	xor    r14,r12

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.96
- Reference cycles: 10.92
- UOPS_RETIRED.ANY: 8.0

Experiment 2 (with additional nop)

Instruction: ADD dword ptr [R14], 16777216
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥7

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 31 e6             	xor    r14,r12
  19:	4d 31 e6             	xor    r14,r12
  1c:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 10.96
- Reference cycles: 10.97
- UOPS_RETIRED.ANY: 9.0

Latency operand 1 → 1 (address, index register): ≤4

Experiment 1

Instruction: ADD dword ptr [R14+R13], 16777216
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥7

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 31 e5             	xor    r13,r12
  1b:	4d 31 e5             	xor    r13,r12

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.96
- Reference cycles: 11.04
- UOPS_RETIRED.ANY: 8.0

Experiment 2 (with additional nop)

Instruction: ADD dword ptr [R14+R13], 16777216
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥7

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 31 e5             	xor    r13,r12
  1b:	4d 31 e5             	xor    r13,r12
  1e:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 10.96
- Reference cycles: 10.98
- UOPS_RETIRED.ANY: 9.0

Latency operand 1 → 1 (memory): 1

Experiment 1

Instruction: ADD dword ptr [R14], 16777216

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 0.99
- Reference cycles: 1.01
- UOPS_RETIRED.ANY: 1.0

Experiment 2

Instruction: ADD dword ptr [R14], 16777216
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOV [R14], R12D
Chain latency: 12

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	4d 63 e4             	movsxd r12,r12d
  28:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 12.99
- Reference cycles: 13.01
- UOPS_RETIRED.ANY: 13.0

Latency operand 1 → 3 (address, base register): 4

Experiment 1

Instruction: ADD dword ptr [R14], 16777216
Chain instruction: CMOVZ R14, R14
Chain latency: 2

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	4d 0f 44 f6          	cmove  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 5.99
- UOPS_RETIRED.ANY: 2.0

Experiment 2

Instruction: ADD dword ptr [R14], 16777216
Chain instruction: CMOVP R14, R14
Chain latency: 2

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	4d 0f 4a f6          	cmovp  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 5.99
- UOPS_RETIRED.ANY: 2.0

Experiment 3

Instruction: ADD dword ptr [R14], 16777216
Chain instruction: CMOVO R14, R14
Chain latency: 2

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	4d 0f 40 f6          	cmovo  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 5.99
- UOPS_RETIRED.ANY: 2.0

Experiment 4

Instruction: ADD dword ptr [R14], 16777216
Chain instruction: CMOVC R14, R14
Chain latency: 2

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	4d 0f 42 f6          	cmovb  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 5.99
- UOPS_RETIRED.ANY: 2.0

Experiment 5

Instruction: ADD dword ptr [R14], 16777216
Chain instruction: CMOVS R14, R14
Chain latency: 2

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	4d 0f 48 f6          	cmovs  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 5.96
- UOPS_RETIRED.ANY: 2.0

Latency operand 1 → 3 (address, index register): 4

Experiment 1

Instruction: ADD dword ptr [R14+R13], 16777216
Chain instruction: CMOVZ R13, R13
Chain latency: 2

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4d 0f 44 ed          	cmove  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 6.0
- UOPS_RETIRED.ANY: 2.0

Experiment 2

Instruction: ADD dword ptr [R14+R13], 16777216
Chain instruction: CMOVP R13, R13
Chain latency: 2

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4d 0f 4a ed          	cmovp  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 6.0
- UOPS_RETIRED.ANY: 2.0

Experiment 3

Instruction: ADD dword ptr [R14+R13], 16777216
Chain instruction: CMOVO R13, R13
Chain latency: 2

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4d 0f 40 ed          	cmovo  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 5.99
- UOPS_RETIRED.ANY: 2.0

Experiment 4

Instruction: ADD dword ptr [R14+R13], 16777216
Chain instruction: CMOVC R13, R13
Chain latency: 2

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4d 0f 42 ed          	cmovb  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 6.0
- UOPS_RETIRED.ANY: 2.0

Experiment 5

Instruction: ADD dword ptr [R14+R13], 16777216
Chain instruction: CMOVS R13, R13
Chain latency: 2

Code:

   0:	43 81 04 2e 00 00 00 	add    DWORD PTR [r14+r13*1],0x1000000
   7:	01 
   8:	4d 0f 48 ed          	cmovs  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 5.99
- UOPS_RETIRED.ANY: 2.0

Latency operand 1 → 3 (memory): ≤1

Experiment 1

Instruction: ADD dword ptr [R14], 16777216
Chain instructions: CMOVZ R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥7

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	4d 0f 44 e4          	cmove  r12,r12
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 8.0
- Reference cycles: 8.09
- UOPS_RETIRED.ANY: 7.0

Experiment 2

Instruction: ADD dword ptr [R14], 16777216
Chain instructions: CMOVP R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥7

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	4d 0f 4a e4          	cmovp  r12,r12
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 8.0
- Reference cycles: 8.06
- UOPS_RETIRED.ANY: 7.0

Experiment 3

Instruction: ADD dword ptr [R14], 16777216
Chain instructions: CMOVO R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥7

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	4d 0f 40 e4          	cmovo  r12,r12
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 8.0
- Reference cycles: 8.0
- UOPS_RETIRED.ANY: 7.0

Experiment 4

Instruction: ADD dword ptr [R14], 16777216
Chain instructions: CMOVC R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥7

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	4d 0f 42 e4          	cmovb  r12,r12
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 8.0
- Reference cycles: 8.01
- UOPS_RETIRED.ANY: 7.0

Experiment 5

Instruction: ADD dword ptr [R14], 16777216
Chain instructions: CMOVS R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥7

Code:

   0:	41 81 06 00 00 00 01 	add    DWORD PTR [r14],0x1000000
   7:	4d 0f 48 e4          	cmovs  r12,r12
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 7.99
- Reference cycles: 7.97
- UOPS_RETIRED.ANY: 7.0

ADD (M32, I32) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤4

Latency operand 1 → 1 (address, index register): ≤4

Latency operand 1 → 1 (memory): 1

Latency operand 1 → 3 (address, base register): 4

Latency operand 1 → 3 (address, index register): 4

Latency operand 1 → 3 (memory): ≤1

Latency operand 1 → 1 (address, base register): ≤4

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤4

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (memory): 1

Experiment 1

Experiment 2

Latency operand 1 → 3 (address, base register): 4

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Latency operand 1 → 3 (address, index register): 4

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Latency operand 1 → 3 (memory): ≤1

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5