ADDSD (XMM, M64)

Experiment 1

Instruction: ADDSD XMM0, qword ptr [R14]

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.96
- Reference cycles: 4.97
- UOPS_RETIRED.ANY: 1.0

Experiment 2

Instruction: ADDSD XMM0, qword ptr [R14]
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.0
- Reference cycles: 14.04
- UOPS_RETIRED.ANY: 10.0

Experiment 3

Instruction: ADDSD XMM0, qword ptr [R14]
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.0
- Reference cycles: 14.03
- UOPS_RETIRED.ANY: 10.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: ADDSD XMM0, qword ptr [R14]

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
ADDSD XMM0, qword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.96
- Reference cycles: 4.94
- UOPS_RETIRED.ANY: 1.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: ADDSD XMM0, qword ptr [R14]
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  14:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  19:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  23:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  28:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  2d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
ADDSD XMM0, qword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.0
- Reference cycles: 14.0
- UOPS_RETIRED.ANY: 10.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: ADDSD XMM0, qword ptr [R14]
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 9

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   a:	66 0f db c0          	pand   xmm0,xmm0
   e:	66 0f db c0          	pand   xmm0,xmm0
  12:	66 0f db c0          	pand   xmm0,xmm0
  16:	66 0f db c0          	pand   xmm0,xmm0
  1a:	66 0f db c0          	pand   xmm0,xmm0
  1e:	66 0f db c0          	pand   xmm0,xmm0
  22:	66 0f db c0          	pand   xmm0,xmm0
  26:	66 0f db c0          	pand   xmm0,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
ADDSD XMM0, qword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 14.0
- Reference cycles: 13.95
- UOPS_RETIRED.ANY: 10.0

Latency operand 2 → 1 (address, base register): ≤10

Experiment 1

Instruction: ADDSD XMM0, qword ptr [R14]
Chain instructions: MOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥9

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	66 49 0f 7e c4       	movq   r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12
  16:	4d 31 e6             	xor    r14,r12
  19:	4d 31 e6             	xor    r14,r12
  1c:	4d 31 e6             	xor    r14,r12
  1f:	4d 31 e6             	xor    r14,r12

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 19.0
- Reference cycles: 19.02
- UOPS_RETIRED.ANY: 10.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: ADDSD XMM0, qword ptr [R14]
Chain instructions: MOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥9

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	66 49 0f 7e c4       	movq   r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12
  16:	4d 31 e6             	xor    r14,r12
  19:	4d 31 e6             	xor    r14,r12
  1c:	4d 31 e6             	xor    r14,r12
  1f:	4d 31 e6             	xor    r14,r12

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
ADDSD XMM0, qword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 19.04
- Reference cycles: 19.05
- UOPS_RETIRED.ANY: 10.0

Latency operand 2 → 1 (address, index register): ≤10

Experiment 1

Instruction: ADDSD XMM0, qword ptr [R14+R13]
Chain instructions: MOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥9

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]
   6:	66 49 0f 7e c4       	movq   r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12
  17:	4d 31 e5             	xor    r13,r12
  1a:	4d 31 e5             	xor    r13,r12
  1d:	4d 31 e5             	xor    r13,r12
  20:	4d 31 e5             	xor    r13,r12

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.97
- Reference cycles: 18.98
- UOPS_RETIRED.ANY: 10.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: ADDSD XMM0, qword ptr [R14+R13]
Chain instructions: MOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥9

Code:

   0:	f2 43 0f 58 04 2e    	addsd  xmm0,QWORD PTR [r14+r13*1]
   6:	66 49 0f 7e c4       	movq   r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12
  17:	4d 31 e5             	xor    r13,r12
  1a:	4d 31 e5             	xor    r13,r12
  1d:	4d 31 e5             	xor    r13,r12
  20:	4d 31 e5             	xor    r13,r12

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
XOR R13, R13;
ADDSD XMM0, qword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 19.0
- Reference cycles: 19.05
- UOPS_RETIRED.ANY: 10.0

Latency operand 2 → 1 (memory): ≤12

Experiment 1

Instruction: ADDSD XMM0, qword ptr [R14]
Chain instructions: SHUFPD XMM13, XMM0, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;MOVSD [R14], XMM13
Chain latency: ≥10

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	66 44 0f c6 e8 00    	shufpd xmm13,xmm0,0x0
   b:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  11:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  17:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  1d:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  23:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  29:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  2f:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  35:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  3b:	f2 45 0f 11 2e       	movsd  QWORD PTR [r14],xmm13

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 12.98
- Core cycles: 326.97
- Reference cycles: 327.0
- UOPS_RETIRED.ANY: 139.7

Experiment 2

Instruction: ADDSD XMM0, qword ptr [R14]
Chain instructions: PSHUFD XMM13, XMM0, 0;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;MOVQ [R14], XMM13
Chain latency: ≥10

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	66 44 0f 70 e8 00    	pshufd xmm13,xmm0,0x0
   b:	66 45 0f db ed       	pand   xmm13,xmm13
  10:	66 45 0f db ed       	pand   xmm13,xmm13
  15:	66 45 0f db ed       	pand   xmm13,xmm13
  1a:	66 45 0f db ed       	pand   xmm13,xmm13
  1f:	66 45 0f db ed       	pand   xmm13,xmm13
  24:	66 45 0f db ed       	pand   xmm13,xmm13
  29:	66 45 0f db ed       	pand   xmm13,xmm13
  2e:	66 45 0f db ed       	pand   xmm13,xmm13
  33:	66 45 0f d6 2e       	movq   QWORD PTR [r14],xmm13

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 21.93
- Reference cycles: 21.98
- UOPS_RETIRED.ANY: 11.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: ADDSD XMM0, qword ptr [R14]
Chain instructions: SHUFPD XMM13, XMM0, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;SHUFPD XMM13, XMM13, 0;MOVSD [R14], XMM13
Chain latency: ≥10

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	66 44 0f c6 e8 00    	shufpd xmm13,xmm0,0x0
   b:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  11:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  17:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  1d:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  23:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  29:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  2f:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  35:	66 45 0f c6 ed 00    	shufpd xmm13,xmm13,0x0
  3b:	f2 45 0f 11 2e       	movsd  QWORD PTR [r14],xmm13

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
ADDSD XMM0, qword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 12.98
- Core cycles: 326.9
- Reference cycles: 326.85
- UOPS_RETIRED.ANY: 139.7

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: ADDSD XMM0, qword ptr [R14]
Chain instructions: PSHUFD XMM13, XMM0, 0;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;PAND XMM13, XMM13;MOVQ [R14], XMM13
Chain latency: ≥10

Code:

   0:	f2 41 0f 58 06       	addsd  xmm0,QWORD PTR [r14]
   5:	66 44 0f 70 e8 00    	pshufd xmm13,xmm0,0x0
   b:	66 45 0f db ed       	pand   xmm13,xmm13
  10:	66 45 0f db ed       	pand   xmm13,xmm13
  15:	66 45 0f db ed       	pand   xmm13,xmm13
  1a:	66 45 0f db ed       	pand   xmm13,xmm13
  1f:	66 45 0f db ed       	pand   xmm13,xmm13
  24:	66 45 0f db ed       	pand   xmm13,xmm13
  29:	66 45 0f db ed       	pand   xmm13,xmm13
  2e:	66 45 0f db ed       	pand   xmm13,xmm13
  33:	66 45 0f d6 2e       	movq   QWORD PTR [r14],xmm13

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
ADDSD XMM0, qword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 21.93
- Reference cycles: 21.92
- UOPS_RETIRED.ANY: 11.0

ADDSD (XMM, M64) - Latency

Operands

Latency operand 1 → 1: 5

Latency operand 2 → 1 (address, base register): ≤10

Latency operand 2 → 1 (address, index register): ≤10

Latency operand 2 → 1 (memory): ≤12

Latency operand 1 → 1: 5

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1 (address, base register): ≤10

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1 (address, index register): ≤10

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1 (memory): ≤12

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)