DIV (M64) - Latency


Operands


Latency operand 1 → 2 (address, base register): 34 ≤ lat ≤ 96

Latency operand 1 → 2 (address, index register): 34 ≤ lat ≤ 96

Latency operand 1 → 3 (address, base register): 33 ≤ lat ≤ 95

Latency operand 1 → 3 (address, index register): 33 ≤ lat ≤ 95

Latency operand 2 → 2: 30 ≤ lat ≤ 92

Latency operand 2 → 3: 31 ≤ lat ≤ 92

Latency operand 3 → 2: 5 ≤ lat ≤ 81

Latency operand 3 → 3: 5 ≤ lat ≤ 78


Latency operand 1 → 2 (address, base register): 34 ≤ lat ≤ 96

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 2 (address, index register): 34 ≤ lat ≤ 96

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, base register): 33 ≤ lat ≤ 95

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, index register): 33 ≤ lat ≤ 95

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 2: 30 ≤ lat ≤ 92

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 3: 31 ≤ lat ≤ 92

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 2: 5 ≤ lat ≤ 81

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 3: 5 ≤ lat ≤ 78

Experiment 1 (fast division)

Experiment 2 (slow division)