SHA256RNDS2 (XMM, XMM)

Experiment 1

Instruction: SHA256RNDS2 XMM0, XMM1

Code:

   0:	0f 38 cb c1          	sha256rnds2 xmm0,xmm1,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 5.0
- Reference cycles: 3.7
- UOPS_EXECUTED.THREAD: 1.0

Experiment 2

Instruction: SHA256RNDS2 XMM0, XMM1
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	0f 38 cb c1          	sha256rnds2 xmm0,xmm1,xmm0
   4:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 7.24
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3

Instruction: SHA256RNDS2 XMM0, XMM1
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	0f 38 cb c1          	sha256rnds2 xmm0,xmm1,xmm0
   4:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 6.9
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: SHA256RNDS2 XMM0, XMM1

Code:

   0:	0f 38 cb c1          	sha256rnds2 xmm0,xmm1,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
SHA256RNDS2 XMM0, XMM1;
SHA256RNDS2 XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 5.0
- Reference cycles: 3.54
- UOPS_EXECUTED.THREAD: 1.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: SHA256RNDS2 XMM0, XMM1
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	0f 38 cb c1          	sha256rnds2 xmm0,xmm1,xmm0
   4:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
SHA256RNDS2 XMM0, XMM1;
SHA256RNDS2 XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 6.9
- UOPS_EXECUTED.THREAD: 6.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: SHA256RNDS2 XMM0, XMM1
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	0f 38 cb c1          	sha256rnds2 xmm0,xmm1,xmm0
   4:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM0, XMM0;
PXOR XMM1, XMM1;
SHA256RNDS2 XMM0, XMM1;
SHA256RNDS2 XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.01
- Reference cycles: 6.57
- UOPS_EXECUTED.THREAD: 6.0

Latency operand 2 → 1: 5

Experiment 1

Instruction: SHA256RNDS2 XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	0f 38 cb c8          	sha256rnds2 xmm1,xmm0,xmm0
   4:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 7.24
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2

Instruction: SHA256RNDS2 XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	0f 38 cb c8          	sha256rnds2 xmm1,xmm0,xmm0
   4:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 7.07
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: SHA256RNDS2 XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	0f 38 cb c8          	sha256rnds2 xmm1,xmm0,xmm0
   4:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
SHA256RNDS2 XMM1, XMM2;
SHA256RNDS2 XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 7.07
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: SHA256RNDS2 XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	0f 38 cb c8          	sha256rnds2 xmm1,xmm0,xmm0
   4:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
SHA256RNDS2 XMM1, XMM2;
SHA256RNDS2 XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 7.07
- UOPS_EXECUTED.THREAD: 6.0

Experiment 5

Instruction: SHA256RNDS2 XMM1, XMM0
Chain instruction: SHA256RNDS2 XMM0, XMM1

Code:

   0:	0f 38 cb c8          	sha256rnds2 xmm1,xmm0,xmm0
   4:	0f 38 cb c1          	sha256rnds2 xmm0,xmm1,xmm0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 10.0
- Reference cycles: 7.24
- UOPS_EXECUTED.THREAD: 2.0

Experiment 6 (with dependency-breaking instructions)

Instruction: SHA256RNDS2 XMM1, XMM0
Chain instructions: SHA256RNDS2 XMM0, XMM1;PXOR XMM1, XMM1

Code:

   0:	0f 38 cb c8          	sha256rnds2 xmm1,xmm0,xmm0
   4:	0f 38 cb c1          	sha256rnds2 xmm0,xmm1,xmm0
   8:	66 0f ef c9          	pxor   xmm1,xmm1

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 9.99
- Reference cycles: 7.07
- UOPS_EXECUTED.THREAD: 2.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: SHA256RNDS2 XMM1, XMM0
Chain instruction: SHA256RNDS2 XMM0, XMM1

Code:

   0:	0f 38 cb c8          	sha256rnds2 xmm1,xmm0,xmm0
   4:	0f 38 cb c1          	sha256rnds2 xmm0,xmm1,xmm0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
SHA256RNDS2 XMM1, XMM2;
SHA256RNDS2 XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 10.0
- Reference cycles: 7.07
- UOPS_EXECUTED.THREAD: 2.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: SHA256RNDS2 XMM1, XMM0
Chain instructions: SHA256RNDS2 XMM0, XMM1;PXOR XMM1, XMM1

Code:

   0:	0f 38 cb c8          	sha256rnds2 xmm1,xmm0,xmm0
   4:	0f 38 cb c1          	sha256rnds2 xmm0,xmm1,xmm0
   8:	66 0f ef c9          	pxor   xmm1,xmm1

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM0, XMM0;
SHA256RNDS2 XMM1, XMM2;
SHA256RNDS2 XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 9.99
- Reference cycles: 6.9
- UOPS_EXECUTED.THREAD: 2.0

Latency operand 3 → 1: 5

Experiment 1

Instruction: SHA256RNDS2 XMM1, XMM2
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	0f 38 cb ca          	sha256rnds2 xmm1,xmm2,xmm0
   4:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 6.9
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2

Instruction: SHA256RNDS2 XMM1, XMM2
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	0f 38 cb ca          	sha256rnds2 xmm1,xmm2,xmm0
   4:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 9.99
- Reference cycles: 7.07
- UOPS_EXECUTED.THREAD: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: SHA256RNDS2 XMM1, XMM2
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	0f 38 cb ca          	sha256rnds2 xmm1,xmm2,xmm0
   4:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM0, XMM0;
SHA256RNDS2 XMM1, XMM2;
SHA256RNDS2 XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 7.41
- UOPS_EXECUTED.THREAD: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: SHA256RNDS2 XMM1, XMM2
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 5

Code:

   0:	0f 38 cb ca          	sha256rnds2 xmm1,xmm2,xmm0
   4:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0

Init:

VZEROALL;
PXOR XMM1, XMM1;
PXOR XMM2, XMM2;
PXOR XMM0, XMM0;
SHA256RNDS2 XMM1, XMM2;
SHA256RNDS2 XMM2, XMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 10.0
- Reference cycles: 6.9
- UOPS_EXECUTED.THREAD: 6.0

SHA256RNDS2 (XMM, XMM) - Latency

Operands

Latency operand 1 → 1: 5

Latency operand 2 → 1: 5

Latency operand 3 → 1: 5

Latency operand 1 → 1: 5

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 5

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1: 5

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)