PDEP (R64, R64, M64)

Experiment 1

Instruction: PDEP R9, R8, qword ptr [R14]
Chain instruction: PDEP R8, R9, qword ptr [R14]

Code:

   0:	c4 42 bb f5 0e       	pdep   r9,r8,QWORD PTR [r14]
   5:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 8.01
- Reference cycles: 6.06
- UOPS_EXECUTED.THREAD: 4.0

Experiment 2

Instruction: PDEP R9, R8, qword ptr [R14]
Chain instructions: MOVSX R8, R9D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 5

Code:

   0:	c4 42 bb f5 0e       	pdep   r9,r8,QWORD PTR [r14]
   5:	4d 63 c1             	movsxd r8,r9d
   8:	4d 63 c0             	movsxd r8,r8d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.17
- Reference cycles: 5.56
- UOPS_EXECUTED.THREAD: 7.0

Latency operand 3 → 1 (address, base register): 7

Experiment 1

Instruction: PDEP R8, R9, qword ptr [R14]
Chain instructions: MOVSX R8, R8D;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8
Chain latency: 5

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]
   5:	4d 63 c0             	movsxd r8,r8d
   8:	4d 31 c6             	xor    r14,r8
   b:	4d 31 c6             	xor    r14,r8
   e:	4d 31 c6             	xor    r14,r8
  11:	4d 31 c6             	xor    r14,r8

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 12.28
- Reference cycles: 8.92
- UOPS_EXECUTED.THREAD: 7.0

Experiment 2 (with clean upper 32 bits)

Instruction: PDEP R8, R9, qword ptr [R14]
Chain instructions: MOVSX R8, R8D;XOR R14, R8;XOR R14, R8;XOR R14, R8;XOR R14, R8
Chain latency: 5

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]
   5:	4d 63 c0             	movsxd r8,r8d
   8:	4d 31 c6             	xor    r14,r8
   b:	4d 31 c6             	xor    r14,r8
   e:	4d 31 c6             	xor    r14,r8
  11:	4d 31 c6             	xor    r14,r8

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV R9D, R9D;

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 12.27
- Reference cycles: 8.75
- UOPS_EXECUTED.THREAD: 7.0

Latency operand 3 → 1 (address, index register): 8

Experiment 1

Instruction: PDEP R8, R9, qword ptr [R14+R13]
Chain instructions: MOVSX R8, R8D;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8
Chain latency: 5

Code:

   0:	c4 02 b3 f5 04 2e    	pdep   r8,r9,QWORD PTR [r14+r13*1]
   6:	4d 63 c0             	movsxd r8,r8d
   9:	4d 31 c5             	xor    r13,r8
   c:	4d 31 c5             	xor    r13,r8
   f:	4d 31 c5             	xor    r13,r8
  12:	4d 31 c5             	xor    r13,r8

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 13.74
- Reference cycles: 10.1
- UOPS_EXECUTED.THREAD: 7.0

Experiment 2 (with clean upper 32 bits)

Instruction: PDEP R8, R9, qword ptr [R14+R13]
Chain instructions: MOVSX R8, R8D;XOR R13, R8;XOR R13, R8;XOR R13, R8;XOR R13, R8
Chain latency: 5

Code:

   0:	c4 02 b3 f5 04 2e    	pdep   r8,r9,QWORD PTR [r14+r13*1]
   6:	4d 63 c0             	movsxd r8,r8d
   9:	4d 31 c5             	xor    r13,r8
   c:	4d 31 c5             	xor    r13,r8
   f:	4d 31 c5             	xor    r13,r8
  12:	4d 31 c5             	xor    r13,r8

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
XOR R13, R13;
MOV R9D, R9D;

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 13.74
- Reference cycles: 9.6
- UOPS_EXECUTED.THREAD: 7.0

Latency operand 3 → 1 (memory): ≤9

Experiment 1

Instruction: PDEP R8, R9, qword ptr [R14]
Chain instructions: MOVSX R12, R8D;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12
Chain latency: ≥4

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]
   5:	4d 63 e0             	movsxd r12,r8d
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 89 26             	mov    QWORD PTR [r14],r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 13.33
- Reference cycles: 9.43
- UOPS_EXECUTED.THREAD: 8.0

Experiment 2 (with clean upper 32 bits)

Instruction: PDEP R8, R9, qword ptr [R14]
Chain instructions: MOVSX R12, R8D;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12
Chain latency: ≥4

Code:

   0:	c4 42 b3 f5 06       	pdep   r8,r9,QWORD PTR [r14]
   5:	4d 63 e0             	movsxd r12,r8d
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 89 26             	mov    QWORD PTR [r14],r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV R9D, R9D;

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 13.43
- Reference cycles: 9.26
- UOPS_EXECUTED.THREAD: 8.0

PDEP (R64, R64, M64) - Latency

Operands

Latency operand 2 → 1: 3

Latency operand 3 → 1 (address, base register): 7

Latency operand 3 → 1 (address, index register): 8

Latency operand 3 → 1 (memory): ≤9

Latency operand 2 → 1: 3

Experiment 1

Experiment 2

Latency operand 3 → 1 (address, base register): 7

Experiment 1

Experiment 2 (with clean upper 32 bits)

Latency operand 3 → 1 (address, index register): 8

Experiment 1

Experiment 2 (with clean upper 32 bits)

Latency operand 3 → 1 (memory): ≤9

Experiment 1

Experiment 2 (with clean upper 32 bits)