IMUL (R64, R64)

Experiment 1 (with R9=0)

Instruction: IMUL R8, R9

Code:

   0:	4d 0f af c1          	imul   r8,r9

Init:
```
MOV R9, 0
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.69
- UOPS_EXECUTED.THREAD: 1.0

Experiment 2 (with R9=1)

Instruction: IMUL R8, R9

Code:

   0:	4d 0f af c1          	imul   r8,r9

Init:
```
MOV R9, 1
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 3.2
- UOPS_EXECUTED.THREAD: 1.0

Experiment 3 (with R9=2)

Instruction: IMUL R8, R9

Code:

   0:	4d 0f af c1          	imul   r8,r9

Init:
```
MOV R9, 2
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 2.69
- UOPS_EXECUTED.THREAD: 1.0

Experiment 4 (with R9=0)

Instruction: IMUL R8, R9
Chain instructions: MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	4d 0f af c1          	imul   r8,r9
   4:	4d 63 c0             	movsxd r8,r8d
   7:	4d 63 c0             	movsxd r8,r8d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d
  16:	4d 63 c0             	movsxd r8,r8d

Init:
```
MOV R9, 0
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.01
- Reference cycles: 8.08
- UOPS_EXECUTED.THREAD: 8.0

Experiment 5 (with R9=1)

Instruction: IMUL R8, R9
Chain instructions: MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	4d 0f af c1          	imul   r8,r9
   4:	4d 63 c0             	movsxd r8,r8d
   7:	4d 63 c0             	movsxd r8,r8d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d
  16:	4d 63 c0             	movsxd r8,r8d

Init:
```
MOV R9, 1
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.01
- Reference cycles: 7.91
- UOPS_EXECUTED.THREAD: 8.0

Experiment 6 (with R9=2)

Instruction: IMUL R8, R9
Chain instructions: MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	4d 0f af c1          	imul   r8,r9
   4:	4d 63 c0             	movsxd r8,r8d
   7:	4d 63 c0             	movsxd r8,r8d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d
  16:	4d 63 c0             	movsxd r8,r8d

Init:
```
MOV R9, 2
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.01
- Reference cycles: 7.74
- UOPS_EXECUTED.THREAD: 8.0

Latency operand 1 → 1, with the same register for different operands: 3

Experiment 7 (with the same register for different operands)

Instruction: IMUL R8, R8

Code:

   0:	4d 0f af c0          	imul   r8,r8

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.01
- Reference cycles: 2.53
- UOPS_EXECUTED.THREAD: 1.0

Experiment 8 (with the same register for different operands)

Instruction: IMUL R8, R8
Chain instructions: MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	4d 0f af c0          	imul   r8,r8
   4:	4d 63 c0             	movsxd r8,r8d
   7:	4d 63 c0             	movsxd r8,r8d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d
  16:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.0
- Reference cycles: 7.07
- UOPS_EXECUTED.THREAD: 8.0

Experiment 9 (with clean upper 32 bits, with the same register for different operands)

Instruction: IMUL R8, R8

Code:

   0:	4d 0f af c0          	imul   r8,r8

Init:
```
MOV R8D, R8D;
```
Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.01
- Reference cycles: 2.19
- UOPS_EXECUTED.THREAD: 1.0

Experiment 10 (with clean upper 32 bits, with the same register for different operands)

Instruction: IMUL R8, R8
Chain instructions: MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	4d 0f af c0          	imul   r8,r8
   4:	4d 63 c0             	movsxd r8,r8d
   7:	4d 63 c0             	movsxd r8,r8d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d
  16:	4d 63 c0             	movsxd r8,r8d

Init:
```
MOV R8D, R8D;
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.0
- Reference cycles: 7.24
- UOPS_EXECUTED.THREAD: 8.0

Latency operand 1 → 3: 4

Experiment 1 (with R9=0)

Instruction: IMUL R8, R9
Chain instructions: CMOVO R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c1          	imul   r8,r9
   4:	4d 0f 40 ff          	cmovo  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Init:
```
MOV R9, 0
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.0
- Reference cycles: 8.92
- UOPS_EXECUTED.THREAD: 9.0

Experiment 2 (with R9=1)

Instruction: IMUL R8, R9
Chain instructions: CMOVO R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c1          	imul   r8,r9
   4:	4d 0f 40 ff          	cmovo  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Init:
```
MOV R9, 1
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.0
- Reference cycles: 8.25
- UOPS_EXECUTED.THREAD: 9.0

Experiment 3 (with R9=2)

Instruction: IMUL R8, R9
Chain instructions: CMOVO R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c1          	imul   r8,r9
   4:	4d 0f 40 ff          	cmovo  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Init:
```
MOV R9, 2
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.0
- Reference cycles: 8.08
- UOPS_EXECUTED.THREAD: 9.0

Experiment 4 (with R9=0)

Instruction: IMUL R8, R9
Chain instructions: CMOVC R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c1          	imul   r8,r9
   4:	4d 0f 42 ff          	cmovb  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Init:
```
MOV R9, 0
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.0
- Reference cycles: 8.42
- UOPS_EXECUTED.THREAD: 9.0

Experiment 5 (with R9=1)

Instruction: IMUL R8, R9
Chain instructions: CMOVC R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c1          	imul   r8,r9
   4:	4d 0f 42 ff          	cmovb  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Init:
```
MOV R9, 1
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.0
- Reference cycles: 8.25
- UOPS_EXECUTED.THREAD: 9.0

Experiment 6 (with R9=2)

Instruction: IMUL R8, R9
Chain instructions: CMOVC R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c1          	imul   r8,r9
   4:	4d 0f 42 ff          	cmovb  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Init:
```
MOV R9, 2
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.0
- Reference cycles: 8.42
- UOPS_EXECUTED.THREAD: 9.0

Latency operand 1 → 3, with the same register for different operands: 3

Experiment 7 (with the same register for different operands)

Instruction: IMUL R8, R8
Chain instructions: CMOVO R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c0          	imul   r8,r8
   4:	4d 0f 40 ff          	cmovo  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 7.91
- UOPS_EXECUTED.THREAD: 9.0

Experiment 8 (with the same register for different operands)

Instruction: IMUL R8, R8
Chain instructions: CMOVC R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c0          	imul   r8,r8
   4:	4d 0f 42 ff          	cmovb  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 7.91
- UOPS_EXECUTED.THREAD: 9.0

Experiment 9 (with clean upper 32 bits, with the same register for different operands)

Instruction: IMUL R8, R8
Chain instructions: CMOVO R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c0          	imul   r8,r8
   4:	4d 0f 40 ff          	cmovo  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Init:
```
MOV R8D, R8D;
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 7.91
- UOPS_EXECUTED.THREAD: 9.0

Experiment 10 (with clean upper 32 bits, with the same register for different operands)

Instruction: IMUL R8, R8
Chain instructions: CMOVC R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c0          	imul   r8,r8
   4:	4d 0f 42 ff          	cmovb  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Init:
```
MOV R8D, R8D;
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 7.91
- UOPS_EXECUTED.THREAD: 9.0

Latency operand 2 → 1: 3

Experiment 1

Instruction: IMUL R9, R8
Chain instructions: MOVSX R8, R9D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	4d 0f af c8          	imul   r9,r8
   4:	4d 63 c1             	movsxd r8,r9d
   7:	4d 63 c0             	movsxd r8,r8d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d
  16:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.0
- Reference cycles: 6.9
- UOPS_EXECUTED.THREAD: 8.0

Experiment 2

Instruction: IMUL R9, R8
Chain instruction: IMUL R8, R9

Code:

   0:	4d 0f af c8          	imul   r9,r8
   4:	4d 0f af c1          	imul   r8,r9

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 6.0
- Reference cycles: 4.04
- UOPS_EXECUTED.THREAD: 2.0

Experiment 3 (with dependency-breaking instructions)

Instruction: IMUL R9, R8
Chain instructions: IMUL R8, R9;MOV R9, 0

Code:

   0:	4d 0f af c8          	imul   r9,r8
   4:	4d 0f af c1          	imul   r8,r9
   8:	49 c7 c1 00 00 00 00 	mov    r9,0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.0
- Reference cycles: 5.05
- UOPS_EXECUTED.THREAD: 3.0

Experiment 4 (with the same register for different operands)

Instruction: IMUL R8, R8

Code:

   0:	4d 0f af c0          	imul   r8,r8

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.01
- Reference cycles: 1.85
- UOPS_EXECUTED.THREAD: 1.0

Experiment 5 (with the same register for different operands)

Instruction: IMUL R8, R8
Chain instructions: MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 7

Code:

   0:	4d 0f af c0          	imul   r8,r8
   4:	4d 63 c0             	movsxd r8,r8d
   7:	4d 63 c0             	movsxd r8,r8d
   a:	4d 63 c0             	movsxd r8,r8d
   d:	4d 63 c0             	movsxd r8,r8d
  10:	4d 63 c0             	movsxd r8,r8d
  13:	4d 63 c0             	movsxd r8,r8d
  16:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.0
- Reference cycles: 7.07
- UOPS_EXECUTED.THREAD: 8.0

Latency operand 2 → 3: 3

Experiment 1

Instruction: IMUL R9, R8
Chain instructions: CMOVO R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c8          	imul   r9,r8
   4:	4d 0f 40 ff          	cmovo  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 7.91
- UOPS_EXECUTED.THREAD: 9.0

Experiment 2

Instruction: IMUL R9, R8
Chain instructions: CMOVC R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c8          	imul   r9,r8
   4:	4d 0f 42 ff          	cmovb  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 8.08
- UOPS_EXECUTED.THREAD: 9.0

Experiment 3 (with the same register for different operands)

Instruction: IMUL R8, R8
Chain instructions: CMOVO R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c0          	imul   r8,r8
   4:	4d 0f 40 ff          	cmovo  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 7.91
- UOPS_EXECUTED.THREAD: 9.0

Experiment 4 (with the same register for different operands)

Instruction: IMUL R8, R8
Chain instructions: CMOVC R15, R15;MOVSX R8, R15D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D;MOVSX R8, R8D
Chain latency: 8

Code:

   0:	4d 0f af c0          	imul   r8,r8
   4:	4d 0f 42 ff          	cmovb  r15,r15
   8:	4d 63 c7             	movsxd r8,r15d
   b:	4d 63 c0             	movsxd r8,r8d
   e:	4d 63 c0             	movsxd r8,r8d
  11:	4d 63 c0             	movsxd r8,r8d
  14:	4d 63 c0             	movsxd r8,r8d
  17:	4d 63 c0             	movsxd r8,r8d
  1a:	4d 63 c0             	movsxd r8,r8d

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 7.91
- UOPS_EXECUTED.THREAD: 9.0

IMUL (R64, R64) - Latency

Operands

Latency operand 1 → 1: 4

Latency operand 1 → 1, with the same register for different operands: 3

Latency operand 1 → 3: 4

Latency operand 1 → 3, with the same register for different operands: 3

Latency operand 2 → 1: 3

Latency operand 2 → 3: 3

Latency operand 1 → 1: 4

Experiment 1 (with R9=0)

Experiment 2 (with R9=1)

Experiment 3 (with R9=2)

Experiment 4 (with R9=0)

Experiment 5 (with R9=1)

Experiment 6 (with R9=2)

Latency operand 1 → 1, with the same register for different operands: 3

Experiment 7 (with the same register for different operands)

Experiment 8 (with the same register for different operands)

Experiment 9 (with clean upper 32 bits, with the same register for different operands)

Experiment 10 (with clean upper 32 bits, with the same register for different operands)

Latency operand 1 → 3: 4

Experiment 1 (with R9=0)

Experiment 2 (with R9=1)

Experiment 3 (with R9=2)

Experiment 4 (with R9=0)

Experiment 5 (with R9=1)

Experiment 6 (with R9=2)

Latency operand 1 → 3, with the same register for different operands: 3

Experiment 7 (with the same register for different operands)

Experiment 8 (with the same register for different operands)

Experiment 9 (with clean upper 32 bits, with the same register for different operands)

Experiment 10 (with clean upper 32 bits, with the same register for different operands)

Latency operand 2 → 1: 3

Experiment 1

Experiment 2

Experiment 3 (with dependency-breaking instructions)

Experiment 4 (with the same register for different operands)

Experiment 5 (with the same register for different operands)

Latency operand 2 → 3: 3

Experiment 1

Experiment 2

Experiment 3 (with the same register for different operands)

Experiment 4 (with the same register for different operands)