PCMPESTRM (XMM, XMM, I8) - Latency


Operands


Latency operand 1 → 6: 6

Latency operand 1 → 7: ≤18

Latency operand 2 → 6: 8

Latency operand 2 → 7: ≤20

Latency operand 4 → 6: ≤17

Latency operand 4 → 7: 20

Latency operand 5 → 6: ≤18

Latency operand 5 → 7: 21


Latency operand 1 → 6: 6

Experiment 1

Experiment 2

Experiment 3 (with clean upper 32 bits)

Experiment 4 (with clean upper 32 bits)


Latency operand 1 → 7: ≤18

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6

Experiment 7

Experiment 8

Experiment 9

Experiment 10

Experiment 11

Experiment 12

Experiment 13

Experiment 14

Experiment 15

Experiment 16

Experiment 17

Experiment 18

Experiment 19

Experiment 20

Experiment 21

Experiment 22

Experiment 23

Experiment 24

Experiment 25

Experiment 26

Experiment 27

Experiment 28

Experiment 29

Experiment 30

Experiment 31

Experiment 32

Experiment 33

Experiment 34

Experiment 35

Experiment 36

Experiment 37

Experiment 38

Experiment 39

Experiment 40

Experiment 41

Experiment 42

Experiment 43

Experiment 44

Experiment 45

Experiment 46

Experiment 47

Experiment 48

Experiment 49

Experiment 50

Experiment 51 (with clean upper 32 bits)

Experiment 52 (with clean upper 32 bits)

Experiment 53 (with clean upper 32 bits)

Experiment 54 (with clean upper 32 bits)

Experiment 55 (with clean upper 32 bits)

Experiment 56 (with clean upper 32 bits)

Experiment 57 (with clean upper 32 bits)

Experiment 58 (with clean upper 32 bits)

Experiment 59 (with clean upper 32 bits)

Experiment 60 (with clean upper 32 bits)

Experiment 61 (with clean upper 32 bits)

Experiment 62 (with clean upper 32 bits)

Experiment 63 (with clean upper 32 bits)

Experiment 64 (with clean upper 32 bits)

Experiment 65 (with clean upper 32 bits)

Experiment 66 (with clean upper 32 bits)

Experiment 67 (with clean upper 32 bits)

Experiment 68 (with clean upper 32 bits)

Experiment 69 (with clean upper 32 bits)

Experiment 70 (with clean upper 32 bits)

Experiment 71 (with clean upper 32 bits)

Experiment 72 (with clean upper 32 bits)

Experiment 73 (with clean upper 32 bits)

Experiment 74 (with clean upper 32 bits)

Experiment 75 (with clean upper 32 bits)

Experiment 76 (with clean upper 32 bits)

Experiment 77 (with clean upper 32 bits)

Experiment 78 (with clean upper 32 bits)

Experiment 79 (with clean upper 32 bits)

Experiment 80 (with clean upper 32 bits)

Experiment 81 (with clean upper 32 bits)

Experiment 82 (with clean upper 32 bits)

Experiment 83 (with clean upper 32 bits)

Experiment 84 (with clean upper 32 bits)

Experiment 85 (with clean upper 32 bits)

Experiment 86 (with clean upper 32 bits)

Experiment 87 (with clean upper 32 bits)

Experiment 88 (with clean upper 32 bits)

Experiment 89 (with clean upper 32 bits)

Experiment 90 (with clean upper 32 bits)

Experiment 91 (with clean upper 32 bits)

Experiment 92 (with clean upper 32 bits)

Experiment 93 (with clean upper 32 bits)

Experiment 94 (with clean upper 32 bits)

Experiment 95 (with clean upper 32 bits)

Experiment 96 (with clean upper 32 bits)

Experiment 97 (with clean upper 32 bits)

Experiment 98 (with clean upper 32 bits)

Experiment 99 (with clean upper 32 bits)

Experiment 100 (with clean upper 32 bits)


Latency operand 2 → 6: 8

Experiment 1

Experiment 2

Experiment 3 (with clean upper 32 bits)

Experiment 4 (with clean upper 32 bits)


Latency operand 2 → 7: ≤20

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6

Experiment 7

Experiment 8

Experiment 9

Experiment 10

Experiment 11

Experiment 12

Experiment 13

Experiment 14

Experiment 15

Experiment 16

Experiment 17

Experiment 18

Experiment 19

Experiment 20

Experiment 21

Experiment 22

Experiment 23

Experiment 24

Experiment 25

Experiment 26

Experiment 27

Experiment 28

Experiment 29

Experiment 30

Experiment 31

Experiment 32

Experiment 33

Experiment 34

Experiment 35

Experiment 36

Experiment 37

Experiment 38

Experiment 39

Experiment 40

Experiment 41

Experiment 42

Experiment 43

Experiment 44

Experiment 45

Experiment 46

Experiment 47

Experiment 48

Experiment 49

Experiment 50

Experiment 51 (with clean upper 32 bits)

Experiment 52 (with clean upper 32 bits)

Experiment 53 (with clean upper 32 bits)

Experiment 54 (with clean upper 32 bits)

Experiment 55 (with clean upper 32 bits)

Experiment 56 (with clean upper 32 bits)

Experiment 57 (with clean upper 32 bits)

Experiment 58 (with clean upper 32 bits)

Experiment 59 (with clean upper 32 bits)

Experiment 60 (with clean upper 32 bits)

Experiment 61 (with clean upper 32 bits)

Experiment 62 (with clean upper 32 bits)

Experiment 63 (with clean upper 32 bits)

Experiment 64 (with clean upper 32 bits)

Experiment 65 (with clean upper 32 bits)

Experiment 66 (with clean upper 32 bits)

Experiment 67 (with clean upper 32 bits)

Experiment 68 (with clean upper 32 bits)

Experiment 69 (with clean upper 32 bits)

Experiment 70 (with clean upper 32 bits)

Experiment 71 (with clean upper 32 bits)

Experiment 72 (with clean upper 32 bits)

Experiment 73 (with clean upper 32 bits)

Experiment 74 (with clean upper 32 bits)

Experiment 75 (with clean upper 32 bits)

Experiment 76 (with clean upper 32 bits)

Experiment 77 (with clean upper 32 bits)

Experiment 78 (with clean upper 32 bits)

Experiment 79 (with clean upper 32 bits)

Experiment 80 (with clean upper 32 bits)

Experiment 81 (with clean upper 32 bits)

Experiment 82 (with clean upper 32 bits)

Experiment 83 (with clean upper 32 bits)

Experiment 84 (with clean upper 32 bits)

Experiment 85 (with clean upper 32 bits)

Experiment 86 (with clean upper 32 bits)

Experiment 87 (with clean upper 32 bits)

Experiment 88 (with clean upper 32 bits)

Experiment 89 (with clean upper 32 bits)

Experiment 90 (with clean upper 32 bits)

Experiment 91 (with clean upper 32 bits)

Experiment 92 (with clean upper 32 bits)

Experiment 93 (with clean upper 32 bits)

Experiment 94 (with clean upper 32 bits)

Experiment 95 (with clean upper 32 bits)

Experiment 96 (with clean upper 32 bits)

Experiment 97 (with clean upper 32 bits)

Experiment 98 (with clean upper 32 bits)

Experiment 99 (with clean upper 32 bits)

Experiment 100 (with clean upper 32 bits)


Latency operand 4 → 6: ≤17

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6

Experiment 7

Experiment 8

Experiment 9

Experiment 10

Experiment 11

Experiment 12

Experiment 13

Experiment 14

Experiment 15

Experiment 16

Experiment 17

Experiment 18

Experiment 19 (with clean upper 32 bits)

Experiment 20 (with clean upper 32 bits)

Experiment 21 (with clean upper 32 bits)

Experiment 22 (with clean upper 32 bits)

Experiment 23 (with clean upper 32 bits)

Experiment 24 (with clean upper 32 bits)

Experiment 25 (with clean upper 32 bits)

Experiment 26 (with clean upper 32 bits)

Experiment 27 (with clean upper 32 bits)

Experiment 28 (with clean upper 32 bits)

Experiment 29 (with clean upper 32 bits)

Experiment 30 (with clean upper 32 bits)

Experiment 31 (with clean upper 32 bits)

Experiment 32 (with clean upper 32 bits)

Experiment 33 (with clean upper 32 bits)

Experiment 34 (with clean upper 32 bits)

Experiment 35 (with clean upper 32 bits)

Experiment 36 (with clean upper 32 bits)


Latency operand 4 → 7: 20

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6 (with clean upper 32 bits)

Experiment 7 (with clean upper 32 bits)

Experiment 8 (with clean upper 32 bits)

Experiment 9 (with clean upper 32 bits)

Experiment 10 (with clean upper 32 bits)


Latency operand 5 → 6: ≤18

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Experiment 6

Experiment 7

Experiment 8

Experiment 9

Experiment 10

Experiment 11

Experiment 12

Experiment 13

Experiment 14

Experiment 15

Experiment 16

Experiment 17

Experiment 18


Latency operand 5 → 7: 21

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5