RCPSS (XMM, XMM)

Experiment 1

Instruction: RCPSS XMM0, XMM1

Code:

   0:	f3 0f 53 c1          	rcpss  xmm0,xmm1

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 1.95
- UOPS_RETIRED.ALL: 1.0

Experiment 2

Instruction: RCPSS XMM0, XMM1
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	f3 0f 53 c1          	rcpss  xmm0,xmm1
   4:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  22:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 5.59
- UOPS_RETIRED.ALL: 8.0

Experiment 3

Instruction: RCPSS XMM0, XMM1
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 7

Code:

   0:	f3 0f 53 c1          	rcpss  xmm0,xmm1
   4:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0
  19:	66 0f db c0          	pand   xmm0,xmm0
  1d:	66 0f db c0          	pand   xmm0,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 5.59
- UOPS_RETIRED.ALL: 8.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: RCPSS XMM0, XMM1

Code:

   0:	f3 0f 53 c1          	rcpss  xmm0,xmm1

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
RCPSS XMM0, XMM1;
RCPSS XMM1, XMM0

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 4.0
- Reference cycles: 1.97
- UOPS_RETIRED.ALL: 1.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: RCPSS XMM0, XMM1
Chain instructions: SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	f3 0f 53 c1          	rcpss  xmm0,xmm1
   4:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  22:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
RCPSS XMM0, XMM1;
RCPSS XMM1, XMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 5.46
- UOPS_RETIRED.ALL: 8.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: RCPSS XMM0, XMM1
Chain instructions: PSHUFD XMM0, XMM0, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 7

Code:

   0:	f3 0f 53 c1          	rcpss  xmm0,xmm1
   4:	66 0f 70 c0 00       	pshufd xmm0,xmm0,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0
  19:	66 0f db c0          	pand   xmm0,xmm0
  1d:	66 0f db c0          	pand   xmm0,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM0, [R14];
MOVUPD XMM1, [R14];
RCPSS XMM0, XMM1;
RCPSS XMM1, XMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 5.46
- UOPS_RETIRED.ALL: 8.0

Experiment 1

Instruction: RCPSS XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	f3 0f 53 c8          	rcpss  xmm1,xmm0
   4:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  22:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM1, [R14];
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 5.46
- UOPS_RETIRED.ALL: 8.0

Experiment 2

Instruction: RCPSS XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 7

Code:

   0:	f3 0f 53 c8          	rcpss  xmm1,xmm0
   4:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0
  19:	66 0f db c0          	pand   xmm0,xmm0
  1d:	66 0f db c0          	pand   xmm0,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM1, [R14];
MOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 5.46
- UOPS_RETIRED.ALL: 8.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: RCPSS XMM1, XMM0
Chain instructions: SHUFPD XMM0, XMM1, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	f3 0f 53 c8          	rcpss  xmm1,xmm0
   4:	66 0f c6 c1 00       	shufpd xmm0,xmm1,0x0
   9:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
   e:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  13:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  18:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1d:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  22:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM1, [R14];
MOVUPD XMM0, [R14];
RCPSS XMM1, XMM0;
RCPSS XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 5.46
- UOPS_RETIRED.ALL: 8.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: RCPSS XMM1, XMM0
Chain instructions: PSHUFD XMM0, XMM1, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: 7

Code:

   0:	f3 0f 53 c8          	rcpss  xmm1,xmm0
   4:	66 0f 70 c1 00       	pshufd xmm0,xmm1,0x0
   9:	66 0f db c0          	pand   xmm0,xmm0
   d:	66 0f db c0          	pand   xmm0,xmm0
  11:	66 0f db c0          	pand   xmm0,xmm0
  15:	66 0f db c0          	pand   xmm0,xmm0
  19:	66 0f db c0          	pand   xmm0,xmm0
  1d:	66 0f db c0          	pand   xmm0,xmm0

Init:

MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOVUPD XMM1, [R14];
MOVUPD XMM0, [R14];
RCPSS XMM1, XMM0;
RCPSS XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 5.46
- UOPS_RETIRED.ALL: 8.0

RCPSS (XMM, XMM) - Latency

Operands

Latency operand 1 → 1: 4

Latency operand 2 → 1: 4

Latency operand 1 → 1: 4

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 4

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)