MOVQ (M64, XMM)

Experiment 1

Instruction: MOVQ qword ptr [R14], XMM0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥7

Code:

   0:	66 41 0f d6 06       	movq   QWORD PTR [r14],xmm0
   5:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12

Init:
```
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.05
- Reference cycles: 5.05
- UOPS_RETIRED.ALL: 8.0

Experiment 2 (with additional nop)

Instruction: MOVQ qword ptr [R14], XMM0
Chain instructions: MOV R12, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥7

Code:

   0:	66 41 0f d6 06       	movq   QWORD PTR [r14],xmm0
   5:	4d 8b 26             	mov    r12,QWORD PTR [r14]
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	90                   	nop

Init:
```
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 10.05
- Reference cycles: 4.96
- UOPS_RETIRED.ALL: 9.0

Latency operand 1 → 1 (address, index register): ≤3

Experiment 1

Instruction: MOVQ qword ptr [R14+R13], XMM0
Chain instructions: MOV R12, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥7

Code:

   0:	66 43 0f d6 04 2e    	movq   QWORD PTR [r14+r13*1],xmm0
   6:	4f 8b 24 2e          	mov    r12,QWORD PTR [r14+r13*1]
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 31 e5             	xor    r13,r12
  19:	4d 31 e5             	xor    r13,r12

Init:
```
PXOR XMM0, XMM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.03
- Reference cycles: 5.01
- UOPS_RETIRED.ALL: 8.0

Experiment 2 (with additional nop)

Instruction: MOVQ qword ptr [R14+R13], XMM0
Chain instructions: MOV R12, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥7

Code:

   0:	66 43 0f d6 04 2e    	movq   QWORD PTR [r14+r13*1],xmm0
   6:	4f 8b 24 2e          	mov    r12,QWORD PTR [r14+r13*1]
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 31 e5             	xor    r13,r12
  19:	4d 31 e5             	xor    r13,r12
  1c:	90                   	nop

Init:
```
PXOR XMM0, XMM0;
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 10.04
- Reference cycles: 5.01
- UOPS_RETIRED.ALL: 9.0

Latency operand 2 → 1: ≤4

Experiment 1

Instruction: MOVQ qword ptr [R14], XMM0
Chain instructions: MOVSD XMM13, [R14];SHUFPD XMM0, XMM13, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0;SHUFPD XMM0, XMM0, 0
Chain latency: ≥6

Code:

   0:	66 41 0f d6 06       	movq   QWORD PTR [r14],xmm0
   5:	f2 45 0f 10 2e       	movsd  xmm13,QWORD PTR [r14]
   a:	66 41 0f c6 c5 00    	shufpd xmm0,xmm13,0x0
  10:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  15:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1a:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0
  1f:	66 0f c6 c0 00       	shufpd xmm0,xmm0,0x0

Init:
```
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 10.0
- Reference cycles: 5.01
- UOPS_RETIRED.ALL: 7.0

Experiment 2

Instruction: MOVQ qword ptr [R14], XMM0
Chain instructions: MOVQ XMM13, [R14];PSHUFD XMM0, XMM13, 0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0;PAND XMM0, XMM0
Chain latency: ≥6

Code:

   0:	66 41 0f d6 06       	movq   QWORD PTR [r14],xmm0
   5:	f3 45 0f 7e 2e       	movq   xmm13,QWORD PTR [r14]
   a:	66 41 0f 70 c5 00    	pshufd xmm0,xmm13,0x0
  10:	66 0f db c0          	pand   xmm0,xmm0
  14:	66 0f db c0          	pand   xmm0,xmm0
  18:	66 0f db c0          	pand   xmm0,xmm0
  1c:	66 0f db c0          	pand   xmm0,xmm0

Init:
```
PXOR XMM0, XMM0
```
Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 12.0
- Reference cycles: 5.94
- UOPS_RETIRED.ALL: 7.0

MOVQ (M64, XMM) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤3

Latency operand 1 → 1 (address, index register): ≤3

Latency operand 2 → 1: ≤4

Latency operand 1 → 1 (address, base register): ≤3

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤3

Experiment 1

Experiment 2 (with additional nop)

Latency operand 2 → 1: ≤4

Experiment 1

Experiment 2