DIV (M64) - Latency


Operands


Latency operand 1 → 2 (address, base register): 37 ≤ lat ≤ 99

Latency operand 1 → 2 (address, index register): 37 ≤ lat ≤ 99

Latency operand 1 → 3 (address, base register): 36 ≤ lat ≤ 98

Latency operand 1 → 3 (address, index register): 36 ≤ lat ≤ 98

Latency operand 2 → 2: 34 ≤ lat ≤ 96

Latency operand 2 → 3: 33 ≤ lat ≤ 95

Latency operand 3 → 2: 32 ≤ lat ≤ 95

Latency operand 3 → 3: 32 ≤ lat ≤ 96


Latency operand 1 → 2 (address, base register): 37 ≤ lat ≤ 99

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 2 (address, index register): 37 ≤ lat ≤ 99

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, base register): 36 ≤ lat ≤ 98

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, index register): 36 ≤ lat ≤ 98

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 2: 34 ≤ lat ≤ 96

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 3: 33 ≤ lat ≤ 95

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 2: 32 ≤ lat ≤ 95

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 3: 32 ≤ lat ≤ 96

Experiment 1 (fast division)

Experiment 2 (slow division)