DIV (M32) - Latency


Operands


Latency operand 1 → 2 (address, base register): 26 ≤ lat ≤ 38

Latency operand 1 → 2 (address, index register): 26 ≤ lat ≤ 38

Latency operand 1 → 3 (address, base register): 27 ≤ lat ≤ 39

Latency operand 1 → 3 (address, index register): 27 ≤ lat ≤ 39

Latency operand 2 → 2: 25 ≤ lat ≤ 37

Latency operand 2 → 3: 26 ≤ lat ≤ 38

Latency operand 3 → 2: 26 ≤ lat ≤ 38

Latency operand 3 → 3: 25 ≤ lat ≤ 37


Latency operand 1 → 2 (address, base register): 26 ≤ lat ≤ 38

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 2 (address, index register): 26 ≤ lat ≤ 38

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, base register): 27 ≤ lat ≤ 39

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, index register): 27 ≤ lat ≤ 39

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 2: 25 ≤ lat ≤ 37

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 3: 26 ≤ lat ≤ 38

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 2: 26 ≤ lat ≤ 38

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 3: 25 ≤ lat ≤ 37

Experiment 1 (fast division)

Experiment 2 (slow division)