VPMULLQ_Z (YMM, K, YMM, YMM)

Experiment 1

Instruction: VPMULLQ YMM0 {K1}{z}, YMM1, YMM2
Chain instruction: VPMOVQ2M K1, YMM0
Chain latency: 3

Code:

   0:	62 f2 f5 a9 40 c2    	vpmullq ymm0{k1}{z},ymm1,ymm2
   6:	62 f2 fe 28 39 c8    	vpmovq2m k1,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.01
- Reference cycles: 13.44
- UOPS_EXECUTED.THREAD: 4.0

Experiment 2

Instruction: VPMULLQ YMM0 {K1}{z}, YMM1, YMM2
Chain instruction: VPTESTNMQ K1 {K1}, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 f2 f5 a9 40 c2    	vpmullq ymm0{k1}{z},ymm1,ymm2
   6:	62 f2 fe 29 27 c8    	vptestnmq k1{k1},ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 13.44
- UOPS_EXECUTED.THREAD: 3.98

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPMULLQ YMM0 {K1}{z}, YMM1, YMM2
Chain instruction: VPMOVQ2M K1, YMM0
Chain latency: 3

Code:

   0:	62 f2 f5 a9 40 c2    	vpmullq ymm0{k1}{z},ymm1,ymm2
   6:	62 f2 fe 28 39 c8    	vpmovq2m k1,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VPMULLQ YMM1  {K1}{z}, YMM0, YMM2;
VPMULLQ YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 13.44
- UOPS_EXECUTED.THREAD: 3.99

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPMULLQ YMM0 {K1}{z}, YMM1, YMM2
Chain instruction: VPTESTNMQ K1 {K1}, YMM0, YMM0
Chain latency: 3

Code:

   0:	62 f2 f5 a9 40 c2    	vpmullq ymm0{k1}{z},ymm1,ymm2
   6:	62 f2 fe 29 27 c8    	vptestnmq k1{k1},ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VXORPS YMM2, YMM2, YMM2;
VPMULLQ YMM1  {K1}{z}, YMM0, YMM2;
VPMULLQ YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.01
- Reference cycles: 13.44
- UOPS_EXECUTED.THREAD: 4.0

Latency operand 3 → 1: 15

Experiment 1

Instruction: VPMULLQ YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	62 f2 fd a9 40 ca    	vpmullq ymm1{k1}{z},ymm0,ymm2
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 20.0
- Reference cycles: 15.84
- UOPS_EXECUTED.THREAD: 7.99

Experiment 2

Instruction: VPMULLQ YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	62 f2 fd a9 40 ca    	vpmullq ymm1{k1}{z},ymm0,ymm2
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 19.99
- Reference cycles: 15.2
- UOPS_EXECUTED.THREAD: 8.02

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPMULLQ YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	62 f2 fd a9 40 ca    	vpmullq ymm1{k1}{z},ymm0,ymm2
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPMULLQ YMM0  {K1}{z}, YMM1, YMM2;
VPMULLQ YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 20.0
- Reference cycles: 15.2
- UOPS_EXECUTED.THREAD: 7.99

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPMULLQ YMM1 {K1}{z}, YMM0, YMM2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	62 f2 fd a9 40 ca    	vpmullq ymm1{k1}{z},ymm0,ymm2
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VXORPS YMM2, YMM2, YMM2;
VPMULLQ YMM0  {K1}{z}, YMM1, YMM2;
VPMULLQ YMM2  {K1}{z}, YMM0, YMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 20.0
- Reference cycles: 14.88
- UOPS_EXECUTED.THREAD: 8.01

Latency operand 4 → 1: 15

Experiment 1

Instruction: VPMULLQ YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	62 f2 ed a9 40 c8    	vpmullq ymm1{k1}{z},ymm2,ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 20.0
- Reference cycles: 14.56
- UOPS_EXECUTED.THREAD: 8.01

Experiment 2

Instruction: VPMULLQ YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	62 f2 ed a9 40 c8    	vpmullq ymm1{k1}{z},ymm2,ymm0
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 20.0
- Reference cycles: 15.2
- UOPS_EXECUTED.THREAD: 7.97

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPMULLQ YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	62 f2 ed a9 40 c8    	vpmullq ymm1{k1}{z},ymm2,ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPMULLQ YMM2  {K1}{z}, YMM0, YMM1;
VPMULLQ YMM0  {K1}{z}, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 20.0
- Reference cycles: 14.88
- UOPS_EXECUTED.THREAD: 7.98

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPMULLQ YMM1 {K1}{z}, YMM2, YMM0
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	62 f2 ed a9 40 c8    	vpmullq ymm1{k1}{z},ymm2,ymm0
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM2, YMM2, YMM2;
VXORPS YMM0, YMM0, YMM0;
VPMULLQ YMM2  {K1}{z}, YMM0, YMM1;
VPMULLQ YMM0  {K1}{z}, YMM1, YMM2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 20.0
- Reference cycles: 15.04
- UOPS_EXECUTED.THREAD: 8.02

VPMULLQ_Z (YMM, K, YMM, YMM) - Latency

Operands

Latency operand 2 → 1: 15

Latency operand 3 → 1: 15

Latency operand 4 → 1: 15

Latency operand 2 → 1: 15

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 15

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 4 → 1: 15

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)