VGATHERDPD (ZMM, K, VSIB

Experiment 1

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instruction: VPCMPD K1, XMM15, XMM15, 7

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.04
- Reference cycles: 2.88
- UOPS_EXECUTED.THREAD: 7.0

Experiment 2

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VPCMPD K1, XMM15, XMM15, 7
Chain latency: 7

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
   e:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  15:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1c:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  23:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  2a:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  31:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  38:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.88
- Reference cycles: 8.64
- UOPS_EXECUTED.THREAD: 14.01

Experiment 3

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPCMPD K1, XMM15, XMM15, 7
Chain latency: 7

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
   d:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  13:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  19:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1f:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  25:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  2b:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  31:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 8.83
- Reference cycles: 6.56
- UOPS_EXECUTED.THREAD: 14.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instruction: VPCMPD K1, XMM15, XMM15, 7

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14;
VGATHERDPD ZMM0  {K1}, [R14+YMM14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 4.01
- Reference cycles: 2.88
- UOPS_EXECUTED.THREAD: 7.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VPCMPD K1, XMM15, XMM15, 7
Chain latency: 7

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
   e:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  15:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1c:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  23:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  2a:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  31:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  38:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14;
VGATHERDPD ZMM0  {K1}, [R14+YMM14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.94
- Reference cycles: 8.64
- UOPS_EXECUTED.THREAD: 14.01

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPCMPD K1, XMM15, XMM15, 7
Chain latency: 7

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
   d:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  13:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  19:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1f:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  25:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  2b:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  31:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14;
VGATHERDPD ZMM0  {K1}, [R14+YMM14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 8.71
- Reference cycles: 6.56
- UOPS_EXECUTED.THREAD: 14.0

Latency operand 1 → 2: 3

Experiment 1

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VMOVUPS ZMM0 {K1}, ZMM14;VPCMPD K1, XMM15, XMM15, 7
Chain latency: 1

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	62 d1 7c 49 10 c6    	vmovups zmm0{k1},zmm14
   d:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.28
- Reference cycles: 3.04
- UOPS_EXECUTED.THREAD: 8.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VMOVUPS ZMM0 {K1}, ZMM14;VPCMPD K1, XMM15, XMM15, 7
Chain latency: 1

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	62 d1 7c 49 10 c6    	vmovups zmm0{k1},zmm14
   d:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14;
VGATHERDPD ZMM0  {K1}, [R14+YMM14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 4.31
- Reference cycles: 3.04
- UOPS_EXECUTED.THREAD: 7.99

Latency operand 2 → 1: 23

Experiment 1

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instruction: VPMOVQ2M K1, ZMM0
Chain latency: 3

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	62 f2 fe 48 39 c8    	vpmovq2m k1,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 26.0
- Reference cycles: 20.0
- UOPS_EXECUTED.THREAD: 6.99

Experiment 2

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instruction: VPTESTNMQ K1 {K1}, ZMM0, ZMM0
Chain latency: 3

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	62 f2 fe 49 27 c8    	vptestnmq k1{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 26.0
- Reference cycles: 19.84
- UOPS_EXECUTED.THREAD: 6.98

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instruction: VPMOVQ2M K1, ZMM0
Chain latency: 3

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	62 f2 fe 48 39 c8    	vpmovq2m k1,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14;
VGATHERDPD ZMM0  {K1}, [R14+YMM14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 26.0
- Reference cycles: 19.36
- UOPS_EXECUTED.THREAD: 7.01

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instruction: VPTESTNMQ K1 {K1}, ZMM0, ZMM0
Chain latency: 3

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	62 f2 fe 49 27 c8    	vptestnmq k1{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14;
VGATHERDPD ZMM0  {K1}, [R14+YMM14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 26.04
- Reference cycles: 19.36
- UOPS_EXECUTED.THREAD: 6.97

Latency operand 2 → 2: 1

Experiment 1

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.01
- Reference cycles: 2.72
- UOPS_EXECUTED.THREAD: 6.0

Experiment 2

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: KMOVQ K1, K1;KMOVQ K1, K1;KMOVQ K1, K1;KMOVQ K1, K1;KMOVQ K1, K1;KMOVQ K1, K1;KMOVQ K1, K1
Chain latency: 7

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	c4 e1 f8 90 c9       	kmovq  k1,k1
   c:	c4 e1 f8 90 c9       	kmovq  k1,k1
  11:	c4 e1 f8 90 c9       	kmovq  k1,k1
  16:	c4 e1 f8 90 c9       	kmovq  k1,k1
  1b:	c4 e1 f8 90 c9       	kmovq  k1,k1
  20:	c4 e1 f8 90 c9       	kmovq  k1,k1
  25:	c4 e1 f8 90 c9       	kmovq  k1,k1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 5.92
- UOPS_EXECUTED.THREAD: 12.98

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14;
VGATHERDPD ZMM0  {K1}, [R14+YMM14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.25
- Reference cycles: 2.24
- UOPS_EXECUTED.THREAD: 5.98

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: KMOVQ K1, K1;KMOVQ K1, K1;KMOVQ K1, K1;KMOVQ K1, K1;KMOVQ K1, K1;KMOVQ K1, K1;KMOVQ K1, K1
Chain latency: 7

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	c4 e1 f8 90 c9       	kmovq  k1,k1
   c:	c4 e1 f8 90 c9       	kmovq  k1,k1
  11:	c4 e1 f8 90 c9       	kmovq  k1,k1
  16:	c4 e1 f8 90 c9       	kmovq  k1,k1
  1b:	c4 e1 f8 90 c9       	kmovq  k1,k1
  20:	c4 e1 f8 90 c9       	kmovq  k1,k1
  25:	c4 e1 f8 90 c9       	kmovq  k1,k1

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14;
VGATHERDPD ZMM0  {K1}, [R14+YMM14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 8.0
- Reference cycles: 6.56
- UOPS_EXECUTED.THREAD: 13.01

Latency operand 3 → 1 (address, base register): ≤25

Experiment 1

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;VPCMPD K1, XMM15, XMM15, 7
Chain latency: ≥7

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   c:	4d 31 e6             	xor    r14,r12
   f:	4d 31 e6             	xor    r14,r12
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	4d 31 e6             	xor    r14,r12
  1b:	4d 31 e6             	xor    r14,r12
  1e:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 32.33
- Reference cycles: 24.32
- UOPS_EXECUTED.THREAD: 14.01

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;VPCMPD K1, XMM15, XMM15, 7
Chain latency: ≥7

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   c:	4d 31 e6             	xor    r14,r12
   f:	4d 31 e6             	xor    r14,r12
  12:	4d 31 e6             	xor    r14,r12
  15:	4d 31 e6             	xor    r14,r12
  18:	4d 31 e6             	xor    r14,r12
  1b:	4d 31 e6             	xor    r14,r12
  1e:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14;
VGATHERDPD ZMM0  {K1}, [R14+YMM14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 32.37
- Reference cycles: 24.48
- UOPS_EXECUTED.THREAD: 13.99

Latency operand 3 → 1 (address, index register): ≤28

Experiment 1

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VPCMPD K1, XMM15, XMM15, 7
Chain latency: ≥6

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   b:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   f:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  13:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  17:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1b:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1f:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 34.3
- Reference cycles: 25.76
- UOPS_EXECUTED.THREAD: 13.01

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VANDPD YMM14, YMM14, YMM0;VPCMPD K1, XMM15, XMM15, 7
Chain latency: ≥6

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   b:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
   f:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  13:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  17:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1b:	c5 0d 54 f0          	vandpd ymm14,ymm14,ymm0
  1f:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14;
VGATHERDPD ZMM0  {K1}, [R14+YMM14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 34.31
- Reference cycles: 25.76
- UOPS_EXECUTED.THREAD: 13.02

Latency operand 3 → 1 (memory): ≤22

Experiment 1

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVSD [R14], XMM13;VPCMPD K1, XMM15, XMM15, 7
Chain latency: ≥8

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   c:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  12:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  18:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1e:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  24:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  2a:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  30:	c4 41 7b 11 2e       	vmovsd QWORD PTR [r14],xmm13
  35:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 30.28
- Reference cycles: 23.04
- UOPS_EXECUTED.THREAD: 15.99

Experiment 2

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVQ [R14], XMM13;VPCMPD K1, XMM15, XMM15, 7
Chain latency: ≥8

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   b:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  10:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  15:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1a:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1f:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  24:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  29:	c4 41 79 d6 2e       	vmovq  QWORD PTR [r14],xmm13
  2e:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 30.97
- Reference cycles: 23.04
- UOPS_EXECUTED.THREAD: 15.98

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVSD [R14], XMM13;VPCMPD K1, XMM15, XMM15, 7
Chain latency: ≥8

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   c:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  12:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  18:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1e:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  24:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  2a:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  30:	c4 41 7b 11 2e       	vmovsd QWORD PTR [r14],xmm13
  35:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14;
VGATHERDPD ZMM0  {K1}, [R14+YMM14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 30.05
- Reference cycles: 22.56
- UOPS_EXECUTED.THREAD: 16.01

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VGATHERDPD ZMM0 {K1}, [R14+YMM14]
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVQ [R14], XMM13;VPCMPD K1, XMM15, XMM15, 7
Chain latency: ≥8

Code:

   0:	62 92 fd 49 92 04 36 	vgatherdpd zmm0{k1},QWORD PTR [r14+ymm14*1]
   7:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   b:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  10:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  15:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1a:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1f:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  24:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  29:	c4 41 79 d6 2e       	vmovq  QWORD PTR [r14],xmm13
  2e:	62 d3 05 08 1f cf 07 	vpcmpd k1,xmm15,xmm15,0x7

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VXORPS YMM14, YMM14, YMM14;
VGATHERDPD ZMM0  {K1}, [R14+YMM14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 30.96
- Reference cycles: 23.04
- UOPS_EXECUTED.THREAD: 15.99

VGATHERDPD (ZMM, K, VSIB_YMM) - Latency

Operands

Latency operand 1 → 1: 1

Latency operand 1 → 2: 3

Latency operand 2 → 1: 23

Latency operand 2 → 2: 1

Latency operand 3 → 1 (address, base register): ≤25

Latency operand 3 → 1 (address, index register): ≤28

Latency operand 3 → 1 (memory): ≤22

Latency operand 1 → 1: 1

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 1 → 2: 3

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 23

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 2: 1

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, base register): ≤25

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, index register): ≤28

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (memory): ≤22

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)