VADDPD (ZMM, K, ZMM, ZMM)

Experiment 1

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.49
- Reference cycles: 2.08
- UOPS_EXECUTED.THREAD: 0.99

Experiment 2

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 7

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  30:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.01
- Reference cycles: 8.48
- UOPS_EXECUTED.THREAD: 8.0

Experiment 3

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 7

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  2a:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.01
- Reference cycles: 7.68
- UOPS_EXECUTED.THREAD: 7.99

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VADDPD ZMM0  {K1}, ZMM1, ZMM2;
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 3.57
- Reference cycles: 2.72
- UOPS_EXECUTED.THREAD: 1.01

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 7

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  30:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VADDPD ZMM0  {K1}, ZMM1, ZMM2;
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.01
- Reference cycles: 9.44
- UOPS_EXECUTED.THREAD: 8.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 7

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  2a:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VADDPD ZMM0  {K1}, ZMM1, ZMM2;
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 10.01
- Reference cycles: 7.68
- UOPS_EXECUTED.THREAD: 7.98

Latency operand 2 → 1: 3

Experiment 1

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2
Chain instruction: VPMOVQ2M K1, ZMM0
Chain latency: 3

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 48 39 c8    	vpmovq2m k1,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.01
- Reference cycles: 5.6
- UOPS_EXECUTED.THREAD: 2.01

Experiment 2 (with dependency-breaking instructions)

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VPMOVQ2M K1, ZMM0;;VMOVUPD ZMM0, ZMM15
Chain latency: 3

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 48 39 c8    	vpmovq2m k1,zmm0
   c:	62 d1 fd 48 10 c7    	vmovupd zmm0,zmm15

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.05
- Reference cycles: 4.16
- UOPS_EXECUTED.THREAD: 2.0

Experiment 3

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2
Chain instruction: VPTESTNMQ K1 {K1}, ZMM0, ZMM0
Chain latency: 3

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 49 27 c8    	vptestnmq k1{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.0
- Reference cycles: 5.6
- UOPS_EXECUTED.THREAD: 1.98

Experiment 4 (with dependency-breaking instructions)

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VPTESTNMQ K1 {K1}, ZMM0, ZMM0;;VMOVUPD ZMM0, ZMM15
Chain latency: 3

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 49 27 c8    	vptestnmq k1{k1},zmm0,zmm0
   c:	62 d1 fd 48 10 c7    	vmovupd zmm0,zmm15

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.96
- Reference cycles: 4.96
- UOPS_EXECUTED.THREAD: 1.99

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2
Chain instruction: VPMOVQ2M K1, ZMM0
Chain latency: 3

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 48 39 c8    	vpmovq2m k1,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VADDPD ZMM0  {K1}, ZMM1, ZMM2;
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.06
- Reference cycles: 4.8
- UOPS_EXECUTED.THREAD: 2.02

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VPMOVQ2M K1, ZMM0;;VMOVUPD ZMM0, ZMM15
Chain latency: 3

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 48 39 c8    	vpmovq2m k1,zmm0
   c:	62 d1 fd 48 10 c7    	vmovupd zmm0,zmm15

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VADDPD ZMM0  {K1}, ZMM1, ZMM2;
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 6.09
- Reference cycles: 4.64
- UOPS_EXECUTED.THREAD: 2.01

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2
Chain instruction: VPTESTNMQ K1 {K1}, ZMM0, ZMM0
Chain latency: 3

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 49 27 c8    	vptestnmq k1{k1},zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VADDPD ZMM0  {K1}, ZMM1, ZMM2;
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 7.92
- Reference cycles: 6.08
- UOPS_EXECUTED.THREAD: 1.98

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VADDPD ZMM0 {K1}, ZMM1, ZMM2
Chain instructions: VPTESTNMQ K1 {K1}, ZMM0, ZMM0;;VMOVUPD ZMM0, ZMM15
Chain latency: 3

Code:

   0:	62 f1 f5 49 58 c2    	vaddpd zmm0{k1},zmm1,zmm2
   6:	62 f2 fe 49 27 c8    	vptestnmq k1{k1},zmm0,zmm0
   c:	62 d1 fd 48 10 c7    	vmovupd zmm0,zmm15

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VADDPD ZMM0  {K1}, ZMM1, ZMM2;
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 7.92
- Reference cycles: 6.08
- UOPS_EXECUTED.THREAD: 2.0

Latency operand 3 → 1: 4

Experiment 1

Instruction: VADDPD ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 7

Code:

   0:	62 f1 fd 49 58 ca    	vaddpd zmm1{k1},zmm0,zmm2
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  30:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.01
- Reference cycles: 8.64
- UOPS_EXECUTED.THREAD: 8.01

Experiment 2 (with dependency-breaking instructions)

Instruction: VADDPD ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;;VMOVUPD ZMM1, ZMM15
Chain latency: 7

Code:

   0:	62 f1 fd 49 58 ca    	vaddpd zmm1{k1},zmm0,zmm2
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  30:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  37:	62 d1 fd 48 10 cf    	vmovupd zmm1,zmm15

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 8.0
- UOPS_EXECUTED.THREAD: 7.99

Experiment 3

Instruction: VADDPD ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 7

Code:

   0:	62 f1 fd 49 58 ca    	vaddpd zmm1{k1},zmm0,zmm2
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  2a:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.01
- Reference cycles: 8.48
- UOPS_EXECUTED.THREAD: 8.01

Experiment 4 (with dependency-breaking instructions)

Instruction: VADDPD ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;;VMOVUPD ZMM1, ZMM15
Chain latency: 7

Code:

   0:	62 f1 fd 49 58 ca    	vaddpd zmm1{k1},zmm0,zmm2
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  2a:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  30:	62 d1 fd 48 10 cf    	vmovupd zmm1,zmm15

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.1
- Reference cycles: 8.0
- UOPS_EXECUTED.THREAD: 8.02

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 7

Code:

   0:	62 f1 fd 49 58 ca    	vaddpd zmm1{k1},zmm0,zmm2
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  30:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM2, [R14];
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM0  {K1}, ZMM1, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.01
- Reference cycles: 8.64
- UOPS_EXECUTED.THREAD: 8.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VADDPD ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;;VMOVUPD ZMM1, ZMM15
Chain latency: 7

Code:

   0:	62 f1 fd 49 58 ca    	vaddpd zmm1{k1},zmm0,zmm2
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  30:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  37:	62 d1 fd 48 10 cf    	vmovupd zmm1,zmm15

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM2, [R14];
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM0  {K1}, ZMM1, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 12.0
- Reference cycles: 9.6
- UOPS_EXECUTED.THREAD: 8.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 7

Code:

   0:	62 f1 fd 49 58 ca    	vaddpd zmm1{k1},zmm0,zmm2
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  2a:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM2, [R14];
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM0  {K1}, ZMM1, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.01
- Reference cycles: 8.16
- UOPS_EXECUTED.THREAD: 7.99

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VADDPD ZMM1 {K1}, ZMM0, ZMM2
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;;VMOVUPD ZMM1, ZMM15
Chain latency: 7

Code:

   0:	62 f1 fd 49 58 ca    	vaddpd zmm1{k1},zmm0,zmm2
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  2a:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  30:	62 d1 fd 48 10 cf    	vmovupd zmm1,zmm15

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM0, [R14];
VMOVUPD ZMM2, [R14];
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM0  {K1}, ZMM1, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.11
- Reference cycles: 8.16
- UOPS_EXECUTED.THREAD: 8.0

Latency operand 4 → 1: 4

Experiment 1

Instruction: VADDPD ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 7

Code:

   0:	62 f1 ed 49 58 c8    	vaddpd zmm1{k1},zmm2,zmm0
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  30:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.0
- Reference cycles: 8.0
- UOPS_EXECUTED.THREAD: 8.01

Experiment 2 (with dependency-breaking instructions)

Instruction: VADDPD ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;;VMOVUPD ZMM1, ZMM15
Chain latency: 7

Code:

   0:	62 f1 ed 49 58 c8    	vaddpd zmm1{k1},zmm2,zmm0
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  30:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  37:	62 d1 fd 48 10 cf    	vmovupd zmm1,zmm15

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.0
- Reference cycles: 8.32
- UOPS_EXECUTED.THREAD: 8.0

Experiment 3

Instruction: VADDPD ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 7

Code:

   0:	62 f1 ed 49 58 c8    	vaddpd zmm1{k1},zmm2,zmm0
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  2a:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.01
- Reference cycles: 8.16
- UOPS_EXECUTED.THREAD: 7.98

Experiment 4 (with dependency-breaking instructions)

Instruction: VADDPD ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;;VMOVUPD ZMM1, ZMM15
Chain latency: 7

Code:

   0:	62 f1 ed 49 58 c8    	vaddpd zmm1{k1},zmm2,zmm0
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  2a:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  30:	62 d1 fd 48 10 cf    	vmovupd zmm1,zmm15

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 10.99
- Reference cycles: 8.96
- UOPS_EXECUTED.THREAD: 8.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0
Chain latency: 7

Code:

   0:	62 f1 ed 49 58 c8    	vaddpd zmm1{k1},zmm2,zmm0
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  30:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM0, [R14];
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1;
VADDPD ZMM0  {K1}, ZMM1, ZMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.01
- Reference cycles: 7.84
- UOPS_EXECUTED.THREAD: 8.03

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VADDPD ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VSHUFPD ZMM0, ZMM1, ZMM1, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;VSHUFPD ZMM0, ZMM0, ZMM0, 0;;VMOVUPD ZMM1, ZMM15
Chain latency: 7

Code:

   0:	62 f1 ed 49 58 c8    	vaddpd zmm1{k1},zmm2,zmm0
   6:	62 f1 f5 48 c6 c1 00 	vshufpd zmm0,zmm1,zmm1,0x0
   d:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  14:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  1b:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  22:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  29:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  30:	62 f1 fd 48 c6 c0 00 	vshufpd zmm0,zmm0,zmm0,0x0
  37:	62 d1 fd 48 10 cf    	vmovupd zmm1,zmm15

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM0, [R14];
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1;
VADDPD ZMM0  {K1}, ZMM1, ZMM2

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 11.01
- Reference cycles: 8.0
- UOPS_EXECUTED.THREAD: 7.97

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0
Chain latency: 7

Code:

   0:	62 f1 ed 49 58 c8    	vaddpd zmm1{k1},zmm2,zmm0
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  2a:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM0, [R14];
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1;
VADDPD ZMM0  {K1}, ZMM1, ZMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 11.01
- Reference cycles: 8.0
- UOPS_EXECUTED.THREAD: 7.99

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VADDPD ZMM1 {K1}, ZMM2, ZMM0
Chain instructions: VPANDD ZMM0, ZMM1, ZMM1;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;VPANDD ZMM0, ZMM0, ZMM0;;VMOVUPD ZMM1, ZMM15
Chain latency: 7

Code:

   0:	62 f1 ed 49 58 c8    	vaddpd zmm1{k1},zmm2,zmm0
   6:	62 f1 75 48 db c1    	vpandd zmm0,zmm1,zmm1
   c:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  12:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  18:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  1e:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  24:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  2a:	62 f1 7d 48 db c0    	vpandd zmm0,zmm0,zmm0
  30:	62 d1 fd 48 10 cf    	vmovupd zmm1,zmm15

Init:

MOV R15, 10000;
L: VADDPS ZMM0, ZMM1, ZMM1;
VADDPS ZMM0, ZMM1, ZMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
MOV [R14+32], RAX;
MOV [R14+40], RAX;
MOV [R14+48], RAX;
MOV [R14+56], RAX;
VMOVUPD ZMM1, [R14];
VMOVUPD ZMM2, [R14];
VMOVUPD ZMM0, [R14];
VADDPD ZMM1  {K1}, ZMM0, ZMM2;
VADDPD ZMM2  {K1}, ZMM0, ZMM1;
VADDPD ZMM0  {K1}, ZMM1, ZMM2

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 10.98
- Reference cycles: 8.32
- UOPS_EXECUTED.THREAD: 8.0

VADDPD (ZMM, K, ZMM, ZMM) - Latency

Operands

Latency operand 1 → 1: 3

Latency operand 2 → 1: 3

Latency operand 3 → 1: 4

Latency operand 4 → 1: 4

Latency operand 1 → 1: 3

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 3

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1: 4

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 4 → 1: 4

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)