VSQRTSS (XMM, XMM, XMM)

Experiment 1

Instruction: VSQRTSS XMM0, XMM2, XMM1
Chain instructions: VORPS XMM2, XMM0, XMM0; VORPS XMM2, XMM2, XMM1; VANDPS XMM2, XMM2, XMM1; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2;
Chain latency: ≥11

Code:

   0:	c5 ea 51 c1          	vsqrtss xmm0,xmm2,xmm1
   4:	c5 f8 56 d0          	vorps  xmm2,xmm0,xmm0
   8:	c5 e8 56 d1          	vorps  xmm2,xmm2,xmm1
   c:	c5 e8 54 d1          	vandps xmm2,xmm2,xmm1
  10:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  14:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  18:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  1c:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  20:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  24:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  28:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  2c:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x72d30ff172d30ff1;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPS XMM2, [R14];
VMOVUPS XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 24.0
- Reference cycles: 24.64
- UOPS_RETIRED.ALL: 12.0

Experiment 2

Instruction: VSQRTSS XMM2, XMM2, XMM0

Code:

   0:	c5 ea 51 d0          	vsqrtss xmm2,xmm2,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPS XMM2, [R14];
VMOVUPS XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 11.0
- Reference cycles: 11.52
- UOPS_RETIRED.ALL: 1.0

Experiment 3

Instruction: VSQRTSS XMM0, XMM2, XMM1
Chain instructions: VORPS XMM2, XMM0, XMM0; VORPS XMM2, XMM2, XMM1; VANDPS XMM2, XMM2, XMM1; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2;
Chain latency: ≥11

Code:

   0:	c5 ea 51 c1          	vsqrtss xmm0,xmm2,xmm1
   4:	c5 f8 56 d0          	vorps  xmm2,xmm0,xmm0
   8:	c5 e8 56 d1          	vorps  xmm2,xmm2,xmm1
   c:	c5 e8 54 d1          	vandps xmm2,xmm2,xmm1
  10:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  14:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  18:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  1c:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  20:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  24:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  28:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  2c:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPS XMM2, [R14];
VMOVUPS XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 24.0
- Reference cycles: 24.64
- UOPS_RETIRED.ALL: 12.0

Experiment 1

Instruction: VSQRTSS XMM0, XMM1, XMM2
Chain instructions: VORPS XMM2, XMM0, XMM0; VORPS XMM2, XMM2, XMM1; VANDPS XMM2, XMM2, XMM1; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2;
Chain latency: ≥11

Code:

   0:	c5 f2 51 c2          	vsqrtss xmm0,xmm1,xmm2
   4:	c5 f8 56 d0          	vorps  xmm2,xmm0,xmm0
   8:	c5 e8 56 d1          	vorps  xmm2,xmm2,xmm1
   c:	c5 e8 54 d1          	vandps xmm2,xmm2,xmm1
  10:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  14:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  18:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  1c:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  20:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  24:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  28:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  2c:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x72d30ff172d30ff1;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPS XMM2, [R14];
VMOVUPS XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 24.0
- Reference cycles: 24.64
- UOPS_RETIRED.ALL: 12.0

Experiment 2

Instruction: VSQRTSS XMM2, XMM0, XMM2

Code:

   0:	c5 fa 51 d2          	vsqrtss xmm2,xmm0,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPS XMM2, [R14];
VMOVUPS XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 11.0
- Reference cycles: 11.52
- UOPS_RETIRED.ALL: 1.0

Experiment 3

Instruction: VSQRTSS XMM0, XMM1, XMM2
Chain instructions: VORPS XMM2, XMM0, XMM0; VORPS XMM2, XMM2, XMM1; VANDPS XMM2, XMM2, XMM1; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2; VORPS XMM2, XMM2, XMM2;
Chain latency: ≥11

Code:

   0:	c5 f2 51 c2          	vsqrtss xmm0,xmm1,xmm2
   4:	c5 f8 56 d0          	vorps  xmm2,xmm0,xmm0
   8:	c5 e8 56 d1          	vorps  xmm2,xmm2,xmm1
   c:	c5 e8 54 d1          	vandps xmm2,xmm2,xmm1
  10:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  14:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  18:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  1c:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  20:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  24:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  28:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2
  2c:	c5 e8 56 d2          	vorps  xmm2,xmm2,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x3f8000003f800000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPS XMM2, [R14];
VMOVUPS XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 12.0
- Core cycles: 24.0
- Reference cycles: 24.48
- UOPS_RETIRED.ALL: 12.0

VSQRTSS (XMM, XMM, XMM) - Latency

Operands

Latency operand 2 → 1: ≤11

Latency operand 3 → 1: ≤11

Latency operand 2 → 1: ≤11

Experiment 1

Experiment 2

Experiment 3

Latency operand 3 → 1: ≤11

Experiment 1

Experiment 2

Experiment 3