VPADDD (YMM, YMM, M256)

Experiment 1

Instruction: VPADDD YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 c1 7d fe 0e       	vpaddd ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.18
- Reference cycles: 7.04
- UOPS_RETIRED.ALL: 12.0

Experiment 2

Instruction: VPADDD YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 c1 7d fe 0e       	vpaddd ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.26
- Reference cycles: 7.68
- UOPS_RETIRED.ALL: 12.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPADDD YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 c1 7d fe 0e       	vpaddd ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
   f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  14:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  19:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VPADDD YMM0, YMM1, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.15
- Reference cycles: 7.52
- UOPS_RETIRED.ALL: 12.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPADDD YMM1, YMM0, ymmword ptr [R14]
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 c1 7d fe 0e       	vpaddd ymm1,ymm0,YMMWORD PTR [r14]
   5:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   9:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   d:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  11:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  15:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VPADDD YMM0, YMM1, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 7.19
- Reference cycles: 7.36
- UOPS_RETIRED.ALL: 12.0

Latency operand 3 → 1 (address, base register): ≤11

Experiment 1

Instruction: VPADDD YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	c4 c1 75 fe 06       	vpaddd ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 16.0
- Reference cycles: 16.16
- UOPS_RETIRED.ALL: 7.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VPADDD YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	c4 c1 75 fe 06       	vpaddd ymm0,ymm1,YMMWORD PTR [r14]
   5:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VPADDD YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 16.0
- Reference cycles: 16.8
- UOPS_RETIRED.ALL: 7.0

Latency operand 3 → 1 (address, index register): ≤11

Experiment 1

Instruction: VPADDD YMM0, YMM1, ymmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	c4 81 75 fe 04 2e    	vpaddd ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 16.0
- Reference cycles: 15.68
- UOPS_RETIRED.ALL: 7.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VPADDD YMM0, YMM1, ymmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	c4 81 75 fe 04 2e    	vpaddd ymm0,ymm1,YMMWORD PTR [r14+r13*1]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13;
VPADDD YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 16.0
- Reference cycles: 16.16
- UOPS_RETIRED.ALL: 7.0

Latency operand 3 → 1 (memory): ≤9

Experiment 1

Instruction: VPADDD YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13
Chain latency: ≥6

Code:

   0:	c4 c1 75 fe 06       	vpaddd ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   a:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  10:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  16:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1c:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  22:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 14.97
- Reference cycles: 15.36
- UOPS_RETIRED.ALL: 14.0

Experiment 2

Instruction: VPADDD YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VPAND YMM13, YMM0, YMM0;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VMOVDQU [R14], YMM13
Chain latency: ≥6

Code:

   0:	c4 c1 75 fe 06       	vpaddd ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d db e8          	vpand  ymm13,ymm0,ymm0
   9:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
   e:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  13:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  18:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  1d:	c4 41 7e 7f 2e       	vmovdqu YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 15.06
- Reference cycles: 16.0
- UOPS_RETIRED.ALL: 14.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VPADDD YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13
Chain latency: ≥6

Code:

   0:	c4 c1 75 fe 06       	vpaddd ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   a:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  10:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  16:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1c:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  22:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VPADDD YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 15.27
- Reference cycles: 15.36
- UOPS_RETIRED.ALL: 14.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VPADDD YMM0, YMM1, ymmword ptr [R14]
Chain instructions: VPAND YMM13, YMM0, YMM0;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VPAND YMM13, YMM13, YMM13;VMOVDQU [R14], YMM13
Chain latency: ≥6

Code:

   0:	c4 c1 75 fe 06       	vpaddd ymm0,ymm1,YMMWORD PTR [r14]
   5:	c5 7d db e8          	vpand  ymm13,ymm0,ymm0
   9:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
   e:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  13:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  18:	c4 41 15 db ed       	vpand  ymm13,ymm13,ymm13
  1d:	c4 41 7e 7f 2e       	vmovdqu YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VPADDD YMM1, YMM0, ymmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 15.5
- Reference cycles: 15.84
- UOPS_RETIRED.ALL: 14.0

VPADDD (YMM, YMM, M256) - Latency

Operands

Latency operand 2 → 1: 2

Latency operand 3 → 1 (address, base register): ≤11

Latency operand 3 → 1 (address, index register): ≤11

Latency operand 3 → 1 (memory): ≤9

Latency operand 2 → 1: 2

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, base register): ≤11

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, index register): ≤11

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (memory): ≤9

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)