VINSERTI128 (YMM, YMM, M128, I8)

Experiment 1

Instruction: VINSERTI128 YMM1, YMM0, xmmword ptr [R14], 2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 c3 7d 38 0e 02    	vinserti128 ymm1,ymm0,XMMWORD PTR [r14],0x2
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.04
- Reference cycles: 8.32
- UOPS_RETIRED.ALL: 12.0

Experiment 2

Instruction: VINSERTI128 YMM1, YMM0, xmmword ptr [R14], 2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 c3 7d 38 0e 02    	vinserti128 ymm1,ymm0,XMMWORD PTR [r14],0x2
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.04
- Reference cycles: 8.64
- UOPS_RETIRED.ALL: 12.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VINSERTI128 YMM1, YMM0, xmmword ptr [R14], 2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 5

Code:

   0:	c4 c3 7d 38 0e 02    	vinserti128 ymm1,ymm0,XMMWORD PTR [r14],0x2
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VINSERTI128 YMM0, YMM1, xmmword ptr [R14], 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.2
- Reference cycles: 8.64
- UOPS_RETIRED.ALL: 12.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VINSERTI128 YMM1, YMM0, xmmword ptr [R14], 2
Chain instructions: VPAND YMM0, YMM1, YMM1;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0;VPAND YMM0, YMM0, YMM0
Chain latency: 5

Code:

   0:	c4 c3 7d 38 0e 02    	vinserti128 ymm1,ymm0,XMMWORD PTR [r14],0x2
   6:	c5 f5 db c1          	vpand  ymm0,ymm1,ymm1
   a:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
   e:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  12:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0
  16:	c5 fd db c0          	vpand  ymm0,ymm0,ymm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM0, YMM0, YMM0;
VINSERTI128 YMM0, YMM1, xmmword ptr [R14], 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 8.04
- Reference cycles: 7.84
- UOPS_RETIRED.ALL: 12.0

Latency operand 3 → 1 (address, base register): ≤11

Experiment 1

Instruction: VINSERTI128 YMM0, YMM1, xmmword ptr [R14], 2
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 16.09
- Reference cycles: 16.48
- UOPS_RETIRED.ALL: 7.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VINSERTI128 YMM0, YMM1, xmmword ptr [R14], 2
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VINSERTI128 YMM1, YMM0, xmmword ptr [R14], 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 16.09
- Reference cycles: 16.64
- UOPS_RETIRED.ALL: 7.0

Latency operand 3 → 1 (address, index register): ≤11

Experiment 1

Instruction: VINSERTI128 YMM0, YMM1, xmmword ptr [R14+R13], 2
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   c:	4d 31 e5             	xor    r13,r12
   f:	4d 31 e5             	xor    r13,r12
  12:	4d 31 e5             	xor    r13,r12
  15:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 16.08
- Reference cycles: 16.16
- UOPS_RETIRED.ALL: 7.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VINSERTI128 YMM0, YMM1, xmmword ptr [R14+R13], 2
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	c4 83 75 38 04 2e 02 	vinserti128 ymm0,ymm1,XMMWORD PTR [r14+r13*1],0x2
   7:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   c:	4d 31 e5             	xor    r13,r12
   f:	4d 31 e5             	xor    r13,r12
  12:	4d 31 e5             	xor    r13,r12
  15:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
XOR R13, R13;
VINSERTI128 YMM1, YMM0, xmmword ptr [R14], 2

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 16.08
- Reference cycles: 16.48
- UOPS_RETIRED.ALL: 7.0

Latency operand 3 → 1 (memory): ≤8

Experiment 1

Instruction: VINSERTI128 YMM0, YMM1, xmmword ptr [R14], 2
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVUPD [R14], XMM13
Chain latency: ≥6

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   b:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  11:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  17:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1d:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  23:	c4 41 79 11 2e       	vmovupd XMMWORD PTR [r14],xmm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 14.59
- Reference cycles: 15.36
- UOPS_RETIRED.ALL: 8.0

Experiment 2

Instruction: VINSERTI128 YMM0, YMM1, xmmword ptr [R14], 2
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVDQU [R14], XMM13
Chain latency: ≥6

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   a:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
   f:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  14:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  19:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1e:	c4 41 7a 7f 2e       	vmovdqu XMMWORD PTR [r14],xmm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 14.58
- Reference cycles: 15.04
- UOPS_RETIRED.ALL: 8.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VINSERTI128 YMM0, YMM1, xmmword ptr [R14], 2
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVUPD [R14], XMM13
Chain latency: ≥6

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   b:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  11:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  17:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1d:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  23:	c4 41 79 11 2e       	vmovupd XMMWORD PTR [r14],xmm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VINSERTI128 YMM1, YMM0, xmmword ptr [R14], 2

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 14.59
- Reference cycles: 15.04
- UOPS_RETIRED.ALL: 8.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VINSERTI128 YMM0, YMM1, xmmword ptr [R14], 2
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVDQU [R14], XMM13
Chain latency: ≥6

Code:

   0:	c4 c3 75 38 06 02    	vinserti128 ymm0,ymm1,XMMWORD PTR [r14],0x2
   6:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   a:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
   f:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  14:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  19:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1e:	c4 41 7a 7f 2e       	vmovdqu XMMWORD PTR [r14],xmm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
VXORPS YMM1, YMM1, YMM1;
VINSERTI128 YMM1, YMM0, xmmword ptr [R14], 2

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 14.58
- Reference cycles: 15.04
- UOPS_RETIRED.ALL: 8.0

VINSERTI128 (YMM, YMM, M128, I8) - Latency

Operands

Latency operand 2 → 1: 3

Latency operand 3 → 1 (address, base register): ≤11

Latency operand 3 → 1 (address, index register): ≤11

Latency operand 3 → 1 (memory): ≤8

Latency operand 2 → 1: 3

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, base register): ≤11

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, index register): ≤11

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (memory): ≤8

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)