VFMADD231PS (XMM, XMM, XMM)

Experiment 1

Instruction: VFMADD231PS XMM0, XMM1, XMM2

Code:

   0:	c4 e2 71 b8 c2       	vfmadd231ps xmm0,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.0
- Reference cycles: 6.24
- UOPS_RETIRED.ALL: 1.0

Experiment 2

Instruction: VFMADD231PS XMM0, XMM1, XMM2
Chain instructions: VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	c4 e2 71 b8 c2       	vfmadd231ps xmm0,xmm1,xmm2
   5:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  23:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  28:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  2d:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 10.0

Experiment 3

Instruction: VFMADD231PS XMM0, XMM1, XMM2
Chain instructions: VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 9

Code:

   0:	c4 e2 71 b8 c2       	vfmadd231ps xmm0,xmm1,xmm2
   5:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  19:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  21:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  25:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 10.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD231PS XMM0, XMM1, XMM2

Code:

   0:	c4 e2 71 b8 c2       	vfmadd231ps xmm0,xmm1,xmm2

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14];
VFMADD231PS XMM0, XMM1, XMM2;
VFMADD231PS XMM1, XMM0, XMM2;
VFMADD231PS XMM2, XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 6.0
- Reference cycles: 5.76
- UOPS_RETIRED.ALL: 1.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD231PS XMM0, XMM1, XMM2
Chain instructions: VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	c4 e2 71 b8 c2       	vfmadd231ps xmm0,xmm1,xmm2
   5:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  23:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  28:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  2d:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14];
VFMADD231PS XMM0, XMM1, XMM2;
VFMADD231PS XMM1, XMM0, XMM2;
VFMADD231PS XMM2, XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 10.0

Experiment 6 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD231PS XMM0, XMM1, XMM2
Chain instructions: VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 9

Code:

   0:	c4 e2 71 b8 c2       	vfmadd231ps xmm0,xmm1,xmm2
   5:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  19:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  21:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  25:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14];
VFMADD231PS XMM0, XMM1, XMM2;
VFMADD231PS XMM1, XMM0, XMM2;
VFMADD231PS XMM2, XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 10.0

Latency operand 2 → 1: 9

Experiment 1

Instruction: VFMADD231PS XMM1, XMM0, XMM2
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	c4 e2 79 b8 ca       	vfmadd231ps xmm1,xmm0,xmm2
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  23:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  28:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  2d:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 10.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VFMADD231PS XMM1, XMM0, XMM2
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;;VMOVUPD XMM1, XMM15
Chain latency: 9

Code:

   0:	c4 e2 79 b8 ca       	vfmadd231ps xmm1,xmm0,xmm2
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  23:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  28:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  2d:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  32:	c5 79 11 f9          	vmovupd xmm1,xmm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 11.0

Experiment 3

Instruction: VFMADD231PS XMM1, XMM0, XMM2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 9

Code:

   0:	c4 e2 79 b8 ca       	vfmadd231ps xmm1,xmm0,xmm2
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  19:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  21:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  25:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 10.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VFMADD231PS XMM1, XMM0, XMM2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;;VMOVUPD XMM1, XMM15
Chain latency: 9

Code:

   0:	c4 e2 79 b8 ca       	vfmadd231ps xmm1,xmm0,xmm2
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  19:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  21:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  25:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  29:	c5 79 11 f9          	vmovupd xmm1,xmm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 11.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD231PS XMM1, XMM0, XMM2
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	c4 e2 79 b8 ca       	vfmadd231ps xmm1,xmm0,xmm2
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  23:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  28:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  2d:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14];
VFMADD231PS XMM1, XMM0, XMM2;
VFMADD231PS XMM0, XMM1, XMM2;
VFMADD231PS XMM2, XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 10.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD231PS XMM1, XMM0, XMM2
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;;VMOVUPD XMM1, XMM15
Chain latency: 9

Code:

   0:	c4 e2 79 b8 ca       	vfmadd231ps xmm1,xmm0,xmm2
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  23:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  28:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  2d:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  32:	c5 79 11 f9          	vmovupd xmm1,xmm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14];
VFMADD231PS XMM1, XMM0, XMM2;
VFMADD231PS XMM0, XMM1, XMM2;
VFMADD231PS XMM2, XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 11.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD231PS XMM1, XMM0, XMM2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 9

Code:

   0:	c4 e2 79 b8 ca       	vfmadd231ps xmm1,xmm0,xmm2
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  19:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  21:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  25:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14];
VFMADD231PS XMM1, XMM0, XMM2;
VFMADD231PS XMM0, XMM1, XMM2;
VFMADD231PS XMM2, XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 10.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD231PS XMM1, XMM0, XMM2
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;;VMOVUPD XMM1, XMM15
Chain latency: 9

Code:

   0:	c4 e2 79 b8 ca       	vfmadd231ps xmm1,xmm0,xmm2
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  19:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  21:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  25:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  29:	c5 79 11 f9          	vmovupd xmm1,xmm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14];
VFMADD231PS XMM1, XMM0, XMM2;
VFMADD231PS XMM0, XMM1, XMM2;
VFMADD231PS XMM2, XMM0, XMM1

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 18.0
- Reference cycles: 18.56
- UOPS_RETIRED.ALL: 11.0

Latency operand 3 → 1: 9

Experiment 1

Instruction: VFMADD231PS XMM1, XMM2, XMM0
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	c4 e2 69 b8 c8       	vfmadd231ps xmm1,xmm2,xmm0
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  23:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  28:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  2d:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 10.0

Experiment 2 (with dependency-breaking instructions)

Instruction: VFMADD231PS XMM1, XMM2, XMM0
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;;VMOVUPD XMM1, XMM15
Chain latency: 9

Code:

   0:	c4 e2 69 b8 c8       	vfmadd231ps xmm1,xmm2,xmm0
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  23:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  28:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  2d:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  32:	c5 79 11 f9          	vmovupd xmm1,xmm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 18.0
- Reference cycles: 18.56
- UOPS_RETIRED.ALL: 11.0

Experiment 3

Instruction: VFMADD231PS XMM1, XMM2, XMM0
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 9

Code:

   0:	c4 e2 69 b8 c8       	vfmadd231ps xmm1,xmm2,xmm0
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  19:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  21:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  25:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.0
- Reference cycles: 18.72
- UOPS_RETIRED.ALL: 10.0

Experiment 4 (with dependency-breaking instructions)

Instruction: VFMADD231PS XMM1, XMM2, XMM0
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;;VMOVUPD XMM1, XMM15
Chain latency: 9

Code:

   0:	c4 e2 69 b8 c8       	vfmadd231ps xmm1,xmm2,xmm0
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  19:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  21:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  25:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  29:	c5 79 11 f9          	vmovupd xmm1,xmm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 11.0

Experiment 5 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD231PS XMM1, XMM2, XMM0
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 9

Code:

   0:	c4 e2 69 b8 c8       	vfmadd231ps xmm1,xmm2,xmm0
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  23:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  28:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  2d:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14];
VFMADD231PS XMM1, XMM0, XMM2;
VFMADD231PS XMM2, XMM0, XMM1;
VFMADD231PS XMM0, XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 10.0

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD231PS XMM1, XMM2, XMM0
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;;VMOVUPD XMM1, XMM15
Chain latency: 9

Code:

   0:	c4 e2 69 b8 c8       	vfmadd231ps xmm1,xmm2,xmm0
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1e:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  23:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  28:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  2d:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  32:	c5 79 11 f9          	vmovupd xmm1,xmm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14];
VFMADD231PS XMM1, XMM0, XMM2;
VFMADD231PS XMM2, XMM0, XMM1;
VFMADD231PS XMM0, XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 18.0
- Reference cycles: 18.56
- UOPS_RETIRED.ALL: 11.0

Experiment 7 (source registers initialized by an instruction of the same kind)

Instruction: VFMADD231PS XMM1, XMM2, XMM0
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 9

Code:

   0:	c4 e2 69 b8 c8       	vfmadd231ps xmm1,xmm2,xmm0
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  19:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  21:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  25:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14];
VFMADD231PS XMM1, XMM0, XMM2;
VFMADD231PS XMM2, XMM0, XMM1;
VFMADD231PS XMM0, XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 10.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 10.0

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Instruction: VFMADD231PS XMM1, XMM2, XMM0
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;;VMOVUPD XMM1, XMM15
Chain latency: 9

Code:

   0:	c4 e2 69 b8 c8       	vfmadd231ps xmm1,xmm2,xmm0
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  19:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  21:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  25:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  29:	c5 79 11 f9          	vmovupd xmm1,xmm15

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14];
VFMADD231PS XMM1, XMM0, XMM2;
VFMADD231PS XMM2, XMM0, XMM1;
VFMADD231PS XMM0, XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 11.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 11.0

VFMADD231PS (XMM, XMM, XMM) - Latency

Operands

Latency operand 1 → 1: 6

Latency operand 2 → 1: 9

Latency operand 3 → 1: 9

Latency operand 1 → 1: 6

Experiment 1

Experiment 2

Experiment 3

Experiment 4 (source registers initialized by an instruction of the same kind)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind)

Latency operand 2 → 1: 9

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Latency operand 3 → 1: 9

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5 (source registers initialized by an instruction of the same kind)

Experiment 6 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)

Experiment 7 (source registers initialized by an instruction of the same kind)

Experiment 8 (source registers initialized by an instruction of the same kind, with dependency-breaking instructions)