VCVTDQ2PS (YMM, YMM) - Latency

Experiment 1

• Instruction: VCVTDQ2PS YMM1, YMM0
• Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
• Chain latency: 5
• Code:

     0:	c5 fc 5b c8          	vcvtdq2ps ymm1,ymm0
     4:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
     9:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
     e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
    13:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
    18:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS YMM0, YMM0, YMM0

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 11.99
  • Reference cycles: 11.84
  • UOPS_RETIRED.ALL: 12.0

Experiment 2 (source registers initialized by an instruction of the same kind)

• Instruction: VCVTDQ2PS YMM1, YMM0
• Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
• Chain latency: 5
• Code:

     0:	c5 fc 5b c8          	vcvtdq2ps ymm1,ymm0
     4:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
     9:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
     e:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
    13:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
    18:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  

• Init:

  MOV R15, 10000;
  L: VADDPS YMM0, YMM1, YMM1;
  VADDPS YMM0, YMM1, YMM1;
  DEC R15;
  JNZ L;
  VZEROALL;
  VXORPS YMM0, YMM0, YMM0;
  VCVTDQ2PS YMM0, YMM1

• Show nanoBench command
• Results:
  • Instructions retired: 6.0
  • Core cycles: 12.0
  • Reference cycles: 12.32
  • UOPS_RETIRED.ALL: 12.0