VCVTDQ2PD (XMM, M64) - Latency


Operands


Latency operand 2 → 1 (address, base register): ≤12

Latency operand 2 → 1 (address, index register): ≤12

Latency operand 2 → 1 (memory): ≤12


Latency operand 2 → 1 (address, base register): ≤12

Experiment 1


Latency operand 2 → 1 (address, index register): ≤12

Experiment 1


Latency operand 2 → 1 (memory): ≤12

Experiment 1

Experiment 2