VBLENDVPS (XMM, XMM, XMM, XMM)

Experiment 1

Instruction: VBLENDVPS XMM1, XMM0, XMM2, XMM3
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	c4 e3 79 4a ca 30    	vblendvps xmm1,xmm0,xmm2,xmm3
   6:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   b:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  10:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  15:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  24:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14];
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.58
- Reference cycles: 12.8
- UOPS_RETIRED.ALL: 11.0

Experiment 2

Instruction: VBLENDVPS XMM1, XMM0, XMM2, XMM3
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 7

Code:

   0:	c4 e3 79 4a ca 30    	vblendvps xmm1,xmm0,xmm2,xmm3
   6:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  12:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  16:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14];
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.56
- Reference cycles: 12.96
- UOPS_RETIRED.ALL: 11.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPS XMM1, XMM0, XMM2, XMM3
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	c4 e3 79 4a ca 30    	vblendvps xmm1,xmm0,xmm2,xmm3
   6:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   b:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  10:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  15:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  24:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14];
VXORPS XMM3, XMM3, XMM3;
VBLENDVPS XMM0, XMM1, XMM2, XMM3;
VBLENDVPS XMM2, XMM0, XMM1, XMM3;
VBLENDVPS XMM3, XMM0, XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.55
- Reference cycles: 12.48
- UOPS_RETIRED.ALL: 11.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPS XMM1, XMM0, XMM2, XMM3
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 7

Code:

   0:	c4 e3 79 4a ca 30    	vblendvps xmm1,xmm0,xmm2,xmm3
   6:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  12:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  16:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VMOVUPD XMM2, [R14];
VXORPS XMM3, XMM3, XMM3;
VBLENDVPS XMM0, XMM1, XMM2, XMM3;
VBLENDVPS XMM2, XMM0, XMM1, XMM3;
VBLENDVPS XMM3, XMM0, XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.53
- Reference cycles: 12.96
- UOPS_RETIRED.ALL: 11.0

Latency operand 3 → 1: 5

Experiment 1

Instruction: VBLENDVPS XMM1, XMM2, XMM0, XMM3
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	c4 e3 69 4a c8 30    	vblendvps xmm1,xmm2,xmm0,xmm3
   6:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   b:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  10:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  15:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  24:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14];
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.58
- Reference cycles: 12.8
- UOPS_RETIRED.ALL: 11.0

Experiment 2

Instruction: VBLENDVPS XMM1, XMM2, XMM0, XMM3
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 7

Code:

   0:	c4 e3 69 4a c8 30    	vblendvps xmm1,xmm2,xmm0,xmm3
   6:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  12:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  16:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14];
VXORPS XMM3, XMM3, XMM3

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.57
- Reference cycles: 13.12
- UOPS_RETIRED.ALL: 11.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPS XMM1, XMM2, XMM0, XMM3
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	c4 e3 69 4a c8 30    	vblendvps xmm1,xmm2,xmm0,xmm3
   6:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   b:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  10:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  15:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  24:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14];
VXORPS XMM3, XMM3, XMM3;
VBLENDVPS XMM2, XMM0, XMM1, XMM3;
VBLENDVPS XMM0, XMM1, XMM2, XMM3;
VBLENDVPS XMM3, XMM0, XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.55
- Reference cycles: 12.8
- UOPS_RETIRED.ALL: 11.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPS XMM1, XMM2, XMM0, XMM3
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 7

Code:

   0:	c4 e3 69 4a c8 30    	vblendvps xmm1,xmm2,xmm0,xmm3
   6:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  12:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  16:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM0, [R14];
VXORPS XMM3, XMM3, XMM3;
VBLENDVPS XMM2, XMM0, XMM1, XMM3;
VBLENDVPS XMM0, XMM1, XMM2, XMM3;
VBLENDVPS XMM3, XMM0, XMM1, XMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.54
- Reference cycles: 12.8
- UOPS_RETIRED.ALL: 11.0

Latency operand 4 → 1: 5

Experiment 1

Instruction: VBLENDVPS XMM1, XMM2, XMM3, XMM0
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	c4 e3 69 4a cb 00    	vblendvps xmm1,xmm2,xmm3,xmm0
   6:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   b:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  10:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  15:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  24:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM3, [R14];
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.59
- Reference cycles: 12.96
- UOPS_RETIRED.ALL: 11.0

Experiment 2

Instruction: VBLENDVPS XMM1, XMM2, XMM3, XMM0
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 7

Code:

   0:	c4 e3 69 4a cb 00    	vblendvps xmm1,xmm2,xmm3,xmm0
   6:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  12:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  16:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM3, [R14];
VXORPS XMM0, XMM0, XMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.58
- Reference cycles: 12.96
- UOPS_RETIRED.ALL: 11.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPS XMM1, XMM2, XMM3, XMM0
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 7

Code:

   0:	c4 e3 69 4a cb 00    	vblendvps xmm1,xmm2,xmm3,xmm0
   6:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   b:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  10:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  15:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  1f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  24:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM3, [R14];
VXORPS XMM0, XMM0, XMM0;
VBLENDVPS XMM2, XMM0, XMM1, XMM3;
VBLENDVPS XMM3, XMM0, XMM1, XMM2;
VBLENDVPS XMM0, XMM1, XMM2, XMM3

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.58
- Reference cycles: 12.64
- UOPS_RETIRED.ALL: 11.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPS XMM1, XMM2, XMM3, XMM0
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 7

Code:

   0:	c4 e3 69 4a cb 00    	vblendvps xmm1,xmm2,xmm3,xmm0
   6:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  12:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  16:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1a:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  1e:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM2, [R14];
VMOVUPD XMM3, [R14];
VXORPS XMM0, XMM0, XMM0;
VBLENDVPS XMM2, XMM0, XMM1, XMM3;
VBLENDVPS XMM3, XMM0, XMM1, XMM2;
VBLENDVPS XMM0, XMM1, XMM2, XMM3

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 12.58
- Reference cycles: 12.96
- UOPS_RETIRED.ALL: 11.0

VBLENDVPS (XMM, XMM, XMM, XMM) - Latency

Operands

Latency operand 2 → 1: 5

Latency operand 3 → 1: 5

Latency operand 4 → 1: 5

Latency operand 2 → 1: 5

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1: 5

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 4 → 1: 5

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)