VBLENDVPD (YMM, YMM, M256, YMM)

Experiment 1

Instruction: VBLENDVPD YMM1, YMM0, ymmword ptr [R14], YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 c3 7d 4b 0e 20    	vblendvpd ymm1,ymm0,YMMWORD PTR [r14],ymm2
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 14.67
- Reference cycles: 14.72
- UOPS_RETIRED.ALL: 22.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPD YMM1, YMM0, ymmword ptr [R14], YMM2
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 c3 7d 4b 0e 20    	vblendvpd ymm1,ymm0,YMMWORD PTR [r14],ymm2
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM0, [R14];
VXORPS YMM2, YMM2, YMM2;
VBLENDVPD YMM0, YMM1, ymmword ptr [R14], YMM2;
VBLENDVPD YMM2, YMM0, ymmword ptr [R14], YMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 14.41
- Reference cycles: 15.04
- UOPS_RETIRED.ALL: 22.0

Latency operand 3 → 1 (address, base register): ≤14

Experiment 1

Instruction: VBLENDVPD YMM0, YMM1, ymmword ptr [R14], YMM2
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥7

Code:

   0:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 21.49
- Reference cycles: 22.24
- UOPS_RETIRED.ALL: 15.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPD YMM0, YMM1, ymmword ptr [R14], YMM2
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥7

Code:

   0:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e6             	xor    r14,r12
   e:	4d 31 e6             	xor    r14,r12
  11:	4d 31 e6             	xor    r14,r12
  14:	4d 31 e6             	xor    r14,r12
  17:	4d 31 e6             	xor    r14,r12
  1a:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
VBLENDVPD YMM1, YMM0, ymmword ptr [R14], YMM2;
VBLENDVPD YMM2, YMM0, ymmword ptr [R14], YMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 21.49
- Reference cycles: 21.92
- UOPS_RETIRED.ALL: 15.0

Latency operand 3 → 1 (address, index register): ≤14

Experiment 1

Instruction: VBLENDVPD YMM0, YMM1, ymmword ptr [R14+R13], YMM2
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥7

Code:

   0:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2
   7:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   c:	4d 31 e5             	xor    r13,r12
   f:	4d 31 e5             	xor    r13,r12
  12:	4d 31 e5             	xor    r13,r12
  15:	4d 31 e5             	xor    r13,r12
  18:	4d 31 e5             	xor    r13,r12
  1b:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 21.17
- Reference cycles: 21.92
- UOPS_RETIRED.ALL: 15.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPD YMM0, YMM1, ymmword ptr [R14+R13], YMM2
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥7

Code:

   0:	c4 83 75 4b 04 2e 20 	vblendvpd ymm0,ymm1,YMMWORD PTR [r14+r13*1],ymm2
   7:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   c:	4d 31 e5             	xor    r13,r12
   f:	4d 31 e5             	xor    r13,r12
  12:	4d 31 e5             	xor    r13,r12
  15:	4d 31 e5             	xor    r13,r12
  18:	4d 31 e5             	xor    r13,r12
  1b:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
XOR R13, R13;
VBLENDVPD YMM1, YMM0, ymmword ptr [R14], YMM2;
VBLENDVPD YMM2, YMM0, ymmword ptr [R14], YMM1

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 21.58
- Reference cycles: 21.76
- UOPS_RETIRED.ALL: 15.0

Latency operand 3 → 1 (memory): ≤13

Experiment 1

Instruction: VBLENDVPD YMM0, YMM1, ymmword ptr [R14], YMM2
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13
Chain latency: ≥8

Code:

   0:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
   6:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   b:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  11:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  17:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1d:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  23:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  29:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  2f:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 21.29
- Reference cycles: 21.76
- UOPS_RETIRED.ALL: 24.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPD YMM0, YMM1, ymmword ptr [R14], YMM2
Chain instructions: VSHUFPD YMM13, YMM0, YMM0, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VSHUFPD YMM13, YMM13, YMM13, 0;VMOVUPD [R14], YMM13
Chain latency: ≥8

Code:

   0:	c4 c3 75 4b 06 20    	vblendvpd ymm0,ymm1,YMMWORD PTR [r14],ymm2
   6:	c5 7d c6 e8 00       	vshufpd ymm13,ymm0,ymm0,0x0
   b:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  11:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  17:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  1d:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  23:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  29:	c4 41 15 c6 ed 00    	vshufpd ymm13,ymm13,ymm13,0x0
  2f:	c4 41 7d 11 2e       	vmovupd YMMWORD PTR [r14],ymm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM1, [R14];
VXORPS YMM2, YMM2, YMM2;
VBLENDVPD YMM1, YMM0, ymmword ptr [R14], YMM2;
VBLENDVPD YMM2, YMM0, ymmword ptr [R14], YMM1

Show nanoBench command
Results:
- Instructions retired: 9.0
- Core cycles: 21.32
- Reference cycles: 21.92
- UOPS_RETIRED.ALL: 24.0

Latency operand 4 → 1: 7

Experiment 1

Instruction: VBLENDVPD YMM1, YMM2, ymmword ptr [R14], YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 c3 6d 4b 0e 00    	vblendvpd ymm1,ymm2,YMMWORD PTR [r14],ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VXORPS YMM0, YMM0, YMM0

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 13.97
- Reference cycles: 14.08
- UOPS_RETIRED.ALL: 22.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VBLENDVPD YMM1, YMM2, ymmword ptr [R14], YMM0
Chain instructions: VSHUFPD YMM0, YMM1, YMM1, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0;VSHUFPD YMM0, YMM0, YMM0, 0
Chain latency: 7

Code:

   0:	c4 c3 6d 4b 0e 00    	vblendvpd ymm1,ymm2,YMMWORD PTR [r14],ymm0
   6:	c5 f5 c6 c1 00       	vshufpd ymm0,ymm1,ymm1,0x0
   b:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  10:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  15:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1a:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  1f:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0
  24:	c5 fd c6 c0 00       	vshufpd ymm0,ymm0,ymm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
MOV [R14+16], RAX;
MOV [R14+24], RAX;
VMOVUPD YMM2, [R14];
VXORPS YMM0, YMM0, YMM0;
VBLENDVPD YMM2, YMM0, ymmword ptr [R14], YMM1;
VBLENDVPD YMM0, YMM1, ymmword ptr [R14], YMM2

Show nanoBench command
Results:
- Instructions retired: 8.0
- Core cycles: 14.17
- Reference cycles: 14.24
- UOPS_RETIRED.ALL: 22.0

VBLENDVPD (YMM, YMM, M256, YMM) - Latency

Operands

Latency operand 2 → 1: 7

Latency operand 3 → 1 (address, base register): ≤14

Latency operand 3 → 1 (address, index register): ≤14

Latency operand 3 → 1 (memory): ≤13

Latency operand 4 → 1: 7

Latency operand 2 → 1: 7

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, base register): ≤14

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, index register): ≤14

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (memory): ≤13

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 4 → 1: 7

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)