VADDPD (XMM, XMM, M128)

Experiment 1

Instruction: VADDPD XMM1, XMM0, xmmword ptr [R14]
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c4 c1 79 58 0e       	vaddpd xmm1,xmm0,XMMWORD PTR [r14]
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 11.0
- Reference cycles: 11.36
- UOPS_RETIRED.ALL: 6.0

Experiment 2

Instruction: VADDPD XMM1, XMM0, xmmword ptr [R14]
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c4 c1 79 58 0e       	vaddpd xmm1,xmm0,XMMWORD PTR [r14]
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 11.0
- Reference cycles: 11.04
- UOPS_RETIRED.ALL: 6.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD XMM1, XMM0, xmmword ptr [R14]
Chain instructions: VSHUFPD XMM0, XMM1, XMM1, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0;VSHUFPD XMM0, XMM0, XMM0, 0
Chain latency: 5

Code:

   0:	c4 c1 79 58 0e       	vaddpd xmm1,xmm0,XMMWORD PTR [r14]
   5:	c5 f1 c6 c1 00       	vshufpd xmm0,xmm1,xmm1,0x0
   a:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
   f:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  14:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0
  19:	c5 f9 c6 c0 00       	vshufpd xmm0,xmm0,xmm0,0x0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VADDPD XMM0, XMM1, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 11.0
- Reference cycles: 11.36
- UOPS_RETIRED.ALL: 6.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD XMM1, XMM0, xmmword ptr [R14]
Chain instructions: VPAND XMM0, XMM1, XMM1;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0;VPAND XMM0, XMM0, XMM0
Chain latency: 5

Code:

   0:	c4 c1 79 58 0e       	vaddpd xmm1,xmm0,XMMWORD PTR [r14]
   5:	c5 f1 db c1          	vpand  xmm0,xmm1,xmm1
   9:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
   d:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  11:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0
  15:	c5 f9 db c0          	vpand  xmm0,xmm0,xmm0

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM0, [R14];
VADDPD XMM0, XMM1, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 11.0
- Reference cycles: 11.2
- UOPS_RETIRED.ALL: 6.0

Latency operand 3 → 1 (address, base register): ≤12

Experiment 1

Instruction: VADDPD XMM0, XMM1, xmmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 17.0
- Reference cycles: 17.12
- UOPS_RETIRED.ALL: 6.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD XMM0, XMM1, xmmword ptr [R14]
Chain instructions: VMOVQ R12, XMM0;XOR R14, R12;XOR R14, R12;XOR R14, R12;XOR R14, R12
Chain latency: ≥5

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   a:	4d 31 e6             	xor    r14,r12
   d:	4d 31 e6             	xor    r14,r12
  10:	4d 31 e6             	xor    r14,r12
  13:	4d 31 e6             	xor    r14,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VADDPD XMM1, XMM0, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 17.0
- Reference cycles: 16.96
- UOPS_RETIRED.ALL: 6.0

Latency operand 3 → 1 (address, index register): ≤12

Experiment 1

Instruction: VADDPD XMM0, XMM1, xmmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 17.0
- Reference cycles: 17.12
- UOPS_RETIRED.ALL: 6.0

Experiment 2 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD XMM0, XMM1, xmmword ptr [R14+R13]
Chain instructions: VMOVQ R12, XMM0;XOR R13, R12;XOR R13, R12;XOR R13, R12;XOR R13, R12
Chain latency: ≥5

Code:

   0:	c4 81 71 58 04 2e    	vaddpd xmm0,xmm1,XMMWORD PTR [r14+r13*1]
   6:	c4 c1 f9 7e c4       	vmovq  r12,xmm0
   b:	4d 31 e5             	xor    r13,r12
   e:	4d 31 e5             	xor    r13,r12
  11:	4d 31 e5             	xor    r13,r12
  14:	4d 31 e5             	xor    r13,r12

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
XOR R13, R13;
VADDPD XMM1, XMM0, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 6.0
- Core cycles: 17.0
- Reference cycles: 17.76
- UOPS_RETIRED.ALL: 6.0

Latency operand 3 → 1 (memory): ≤12

Experiment 1

Instruction: VADDPD XMM0, XMM1, xmmword ptr [R14]
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVUPD [R14], XMM13
Chain latency: ≥6

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   a:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  10:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  16:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1c:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  22:	c4 41 79 11 2e       	vmovupd XMMWORD PTR [r14],xmm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 7.0

Experiment 2

Instruction: VADDPD XMM0, XMM1, xmmword ptr [R14]
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVDQU [R14], XMM13
Chain latency: ≥6

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   9:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
   e:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  13:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  18:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1d:	c4 41 7a 7f 2e       	vmovdqu XMMWORD PTR [r14],xmm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 7.0

Experiment 3 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD XMM0, XMM1, xmmword ptr [R14]
Chain instructions: VSHUFPD XMM13, XMM0, XMM0, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VSHUFPD XMM13, XMM13, XMM13, 0;VMOVUPD [R14], XMM13
Chain latency: ≥6

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c5 79 c6 e8 00       	vshufpd xmm13,xmm0,xmm0,0x0
   a:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  10:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  16:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  1c:	c4 41 11 c6 ed 00    	vshufpd xmm13,xmm13,xmm13,0x0
  22:	c4 41 79 11 2e       	vmovupd XMMWORD PTR [r14],xmm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VADDPD XMM1, XMM0, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 7.0

Experiment 4 (source registers initialized by an instruction of the same kind)

Instruction: VADDPD XMM0, XMM1, xmmword ptr [R14]
Chain instructions: VPAND XMM13, XMM0, XMM0;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VPAND XMM13, XMM13, XMM13;VMOVDQU [R14], XMM13
Chain latency: ≥6

Code:

   0:	c4 c1 71 58 06       	vaddpd xmm0,xmm1,XMMWORD PTR [r14]
   5:	c5 79 db e8          	vpand  xmm13,xmm0,xmm0
   9:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
   e:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  13:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  18:	c4 41 11 db ed       	vpand  xmm13,xmm13,xmm13
  1d:	c4 41 7a 7f 2e       	vmovdqu XMMWORD PTR [r14],xmm13

Init:

MOV R15, 10000;
L: VADDPS YMM0, YMM1, YMM1;
VADDPS YMM0, YMM1, YMM1;
DEC R15;
JNZ L;
VZEROALL;
MOV RAX, 0x4000000040000000;
MOV [R14+0], RAX;
MOV [R14+8], RAX;
VMOVUPD XMM1, [R14];
VADDPD XMM1, XMM0, xmmword ptr [R14]

Show nanoBench command
Results:
- Instructions retired: 7.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 7.0

VADDPD (XMM, XMM, M128) - Latency

Operands

Latency operand 2 → 1: 6

Latency operand 3 → 1 (address, base register): ≤12

Latency operand 3 → 1 (address, index register): ≤12

Latency operand 3 → 1 (memory): ≤12

Latency operand 2 → 1: 6

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, base register): ≤12

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (address, index register): ≤12

Experiment 1

Experiment 2 (source registers initialized by an instruction of the same kind)

Latency operand 3 → 1 (memory): ≤12

Experiment 1

Experiment 2

Experiment 3 (source registers initialized by an instruction of the same kind)

Experiment 4 (source registers initialized by an instruction of the same kind)