INC_LOCK (M32)

Experiment 1

Instruction: LOCK INC dword ptr [R14]
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12
Chain latency: ≥22

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	4d 63 e4             	movsxd r12,r12d
  28:	4d 63 e4             	movsxd r12,r12d
  2b:	4d 63 e4             	movsxd r12,r12d
  2e:	4d 63 e4             	movsxd r12,r12d
  31:	4d 63 e4             	movsxd r12,r12d
  34:	4d 63 e4             	movsxd r12,r12d
  37:	4d 63 e4             	movsxd r12,r12d
  3a:	4d 63 e4             	movsxd r12,r12d
  3d:	4d 63 e4             	movsxd r12,r12d
  40:	4d 63 e4             	movsxd r12,r12d
  43:	4d 31 e6             	xor    r14,r12
  46:	4d 31 e6             	xor    r14,r12

Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 42.83
- Reference cycles: 44.32
- UOPS_RETIRED.ALL: 24.0

Experiment 2 (with additional nop)

Instruction: LOCK INC dword ptr [R14]
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R14, R12; XOR R14, R12;nop
Chain latency: ≥22

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	4d 63 e4             	movsxd r12,r12d
  28:	4d 63 e4             	movsxd r12,r12d
  2b:	4d 63 e4             	movsxd r12,r12d
  2e:	4d 63 e4             	movsxd r12,r12d
  31:	4d 63 e4             	movsxd r12,r12d
  34:	4d 63 e4             	movsxd r12,r12d
  37:	4d 63 e4             	movsxd r12,r12d
  3a:	4d 63 e4             	movsxd r12,r12d
  3d:	4d 63 e4             	movsxd r12,r12d
  40:	4d 63 e4             	movsxd r12,r12d
  43:	4d 31 e6             	xor    r14,r12
  46:	4d 31 e6             	xor    r14,r12
  49:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 42.83
- Reference cycles: 43.68
- UOPS_RETIRED.ALL: 25.0

Latency operand 1 → 1 (address, index register): ≤21

Experiment 1

Instruction: LOCK INC dword ptr [R14+R13]
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12
Chain latency: ≥22

Code:

   0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]
   5:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	4d 63 e4             	movsxd r12,r12d
  24:	4d 63 e4             	movsxd r12,r12d
  27:	4d 63 e4             	movsxd r12,r12d
  2a:	4d 63 e4             	movsxd r12,r12d
  2d:	4d 63 e4             	movsxd r12,r12d
  30:	4d 63 e4             	movsxd r12,r12d
  33:	4d 63 e4             	movsxd r12,r12d
  36:	4d 63 e4             	movsxd r12,r12d
  39:	4d 63 e4             	movsxd r12,r12d
  3c:	4d 63 e4             	movsxd r12,r12d
  3f:	4d 63 e4             	movsxd r12,r12d
  42:	4d 63 e4             	movsxd r12,r12d
  45:	4d 31 e5             	xor    r13,r12
  48:	4d 31 e5             	xor    r13,r12

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 24.0
- Core cycles: 42.83
- Reference cycles: 43.68
- UOPS_RETIRED.ALL: 24.0

Experiment 2 (with additional nop)

Instruction: LOCK INC dword ptr [R14+R13]
Chain instructions: MOV R12D, [R14+R13];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;XOR R13, R12; XOR R13, R12;nop
Chain latency: ≥22

Code:

   0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]
   5:	47 8b 24 2e          	mov    r12d,DWORD PTR [r14+r13*1]
   9:	4d 63 e4             	movsxd r12,r12d
   c:	4d 63 e4             	movsxd r12,r12d
   f:	4d 63 e4             	movsxd r12,r12d
  12:	4d 63 e4             	movsxd r12,r12d
  15:	4d 63 e4             	movsxd r12,r12d
  18:	4d 63 e4             	movsxd r12,r12d
  1b:	4d 63 e4             	movsxd r12,r12d
  1e:	4d 63 e4             	movsxd r12,r12d
  21:	4d 63 e4             	movsxd r12,r12d
  24:	4d 63 e4             	movsxd r12,r12d
  27:	4d 63 e4             	movsxd r12,r12d
  2a:	4d 63 e4             	movsxd r12,r12d
  2d:	4d 63 e4             	movsxd r12,r12d
  30:	4d 63 e4             	movsxd r12,r12d
  33:	4d 63 e4             	movsxd r12,r12d
  36:	4d 63 e4             	movsxd r12,r12d
  39:	4d 63 e4             	movsxd r12,r12d
  3c:	4d 63 e4             	movsxd r12,r12d
  3f:	4d 63 e4             	movsxd r12,r12d
  42:	4d 63 e4             	movsxd r12,r12d
  45:	4d 31 e5             	xor    r13,r12
  48:	4d 31 e5             	xor    r13,r12
  4b:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 42.83
- Reference cycles: 43.68
- UOPS_RETIRED.ALL: 25.0

Latency operand 1 → 1 (memory): 18

Experiment 1

Instruction: LOCK INC dword ptr [R14]

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 17.97
- Reference cycles: 18.56
- UOPS_RETIRED.ALL: 1.0

Experiment 2

Instruction: LOCK INC dword ptr [R14]
Chain instructions: MOV R12D, [R14];MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOVSX R12, R12D;MOV [R14], R12D
Chain latency: 10

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	45 8b 26             	mov    r12d,DWORD PTR [r14]
   7:	4d 63 e4             	movsxd r12,r12d
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 30.42
- Reference cycles: 31.2
- UOPS_RETIRED.ALL: 13.0

Latency operand 1 → 2 (address, base register): 16

Experiment 1

Instruction: LOCK INC dword ptr [R14]
Chain instruction: CMOVS R14, R14
Chain latency: 2

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	4d 0f 48 f6          	cmovs  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 2.0

Experiment 2 (with dependency-breaking instructions)

Instruction: LOCK INC dword ptr [R14]
Chain instructions: CMOVS R14, R14;MOV dword ptr [R14], 0
Chain latency: 2

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	4d 0f 48 f6          	cmovs  r14,r14
   8:	41 c7 06 00 00 00 00 	mov    DWORD PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 34.0
- Reference cycles: 34.88
- UOPS_RETIRED.ALL: 3.0

Experiment 3

Instruction: LOCK INC dword ptr [R14]
Chain instruction: CMOVO R14, R14
Chain latency: 2

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	4d 0f 40 f6          	cmovo  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 2.0

Experiment 4 (with dependency-breaking instructions)

Instruction: LOCK INC dword ptr [R14]
Chain instructions: CMOVO R14, R14;MOV dword ptr [R14], 0
Chain latency: 2

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	4d 0f 40 f6          	cmovo  r14,r14
   8:	41 c7 06 00 00 00 00 	mov    DWORD PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 34.0
- Reference cycles: 34.72
- UOPS_RETIRED.ALL: 3.0

Experiment 5

Instruction: LOCK INC dword ptr [R14]
Chain instruction: CMOVP R14, R14
Chain latency: 2

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	4d 0f 4a f6          	cmovp  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 2.0

Experiment 6 (with dependency-breaking instructions)

Instruction: LOCK INC dword ptr [R14]
Chain instructions: CMOVP R14, R14;MOV dword ptr [R14], 0
Chain latency: 2

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	4d 0f 4a f6          	cmovp  r14,r14
   8:	41 c7 06 00 00 00 00 	mov    DWORD PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 34.0
- Reference cycles: 34.72
- UOPS_RETIRED.ALL: 3.0

Experiment 7

Instruction: LOCK INC dword ptr [R14]
Chain instruction: CMOVZ R14, R14
Chain latency: 2

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	4d 0f 44 f6          	cmove  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 2.0

Experiment 8 (with dependency-breaking instructions)

Instruction: LOCK INC dword ptr [R14]
Chain instructions: CMOVZ R14, R14;MOV dword ptr [R14], 0
Chain latency: 2

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	4d 0f 44 f6          	cmove  r14,r14
   8:	41 c7 06 00 00 00 00 	mov    DWORD PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 34.0
- Reference cycles: 34.56
- UOPS_RETIRED.ALL: 3.0

Latency operand 1 → 2 (address, index register): 16

Experiment 1

Instruction: LOCK INC dword ptr [R14+R13]
Chain instruction: CMOVS R13, R13
Chain latency: 2

Code:

   0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]
   5:	4d 0f 48 ed          	cmovs  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 2.0

Experiment 2 (with dependency-breaking instructions)

Instruction: LOCK INC dword ptr [R14+R13]
Chain instructions: CMOVS R13, R13;MOV dword ptr [R14], 0
Chain latency: 2

Code:

   0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]
   5:	4d 0f 48 ed          	cmovs  r13,r13
   9:	41 c7 06 00 00 00 00 	mov    DWORD PTR [r14],0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 19.0
- Reference cycles: 19.52
- UOPS_RETIRED.ALL: 3.0

Experiment 3

Instruction: LOCK INC dword ptr [R14+R13]
Chain instruction: CMOVO R13, R13
Chain latency: 2

Code:

   0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]
   5:	4d 0f 40 ed          	cmovo  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 2.0

Experiment 4 (with dependency-breaking instructions)

Instruction: LOCK INC dword ptr [R14+R13]
Chain instructions: CMOVO R13, R13;MOV dword ptr [R14], 0
Chain latency: 2

Code:

   0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]
   5:	4d 0f 40 ed          	cmovo  r13,r13
   9:	41 c7 06 00 00 00 00 	mov    DWORD PTR [r14],0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 19.0
- Reference cycles: 19.52
- UOPS_RETIRED.ALL: 3.0

Experiment 5

Instruction: LOCK INC dword ptr [R14+R13]
Chain instruction: CMOVP R13, R13
Chain latency: 2

Code:

   0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]
   5:	4d 0f 4a ed          	cmovp  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 2.0

Experiment 6 (with dependency-breaking instructions)

Instruction: LOCK INC dword ptr [R14+R13]
Chain instructions: CMOVP R13, R13;MOV dword ptr [R14], 0
Chain latency: 2

Code:

   0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]
   5:	4d 0f 4a ed          	cmovp  r13,r13
   9:	41 c7 06 00 00 00 00 	mov    DWORD PTR [r14],0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 19.0
- Reference cycles: 19.2
- UOPS_RETIRED.ALL: 3.0

Experiment 7

Instruction: LOCK INC dword ptr [R14+R13]
Chain instruction: CMOVZ R13, R13
Chain latency: 2

Code:

   0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]
   5:	4d 0f 44 ed          	cmove  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.72
- UOPS_RETIRED.ALL: 2.0

Experiment 8 (with dependency-breaking instructions)

Instruction: LOCK INC dword ptr [R14+R13]
Chain instructions: CMOVZ R13, R13;MOV dword ptr [R14], 0
Chain latency: 2

Code:

   0:	f0 43 ff 04 2e       	lock inc DWORD PTR [r14+r13*1]
   5:	4d 0f 44 ed          	cmove  r13,r13
   9:	41 c7 06 00 00 00 00 	mov    DWORD PTR [r14],0x0

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 19.0
- Reference cycles: 19.36
- UOPS_RETIRED.ALL: 3.0

Latency operand 1 → 2 (memory): ≤15

Experiment 1

Instruction: LOCK INC dword ptr [R14]
Chain instructions: CMOVS R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥22

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	4d 0f 48 e4          	cmovs  r12,r12
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	4d 63 e4             	movsxd r12,r12d
  29:	4d 63 e4             	movsxd r12,r12d
  2c:	4d 63 e4             	movsxd r12,r12d
  2f:	4d 63 e4             	movsxd r12,r12d
  32:	4d 63 e4             	movsxd r12,r12d
  35:	4d 63 e4             	movsxd r12,r12d
  38:	4d 63 e4             	movsxd r12,r12d
  3b:	4d 63 e4             	movsxd r12,r12d
  3e:	4d 63 e4             	movsxd r12,r12d
  41:	4d 63 e4             	movsxd r12,r12d
  44:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 23.0
- Core cycles: 37.0
- Reference cycles: 38.08
- UOPS_RETIRED.ALL: 23.0

Experiment 2

Instruction: LOCK INC dword ptr [R14]
Chain instructions: CMOVO R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥22

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	4d 0f 40 e4          	cmovo  r12,r12
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	4d 63 e4             	movsxd r12,r12d
  29:	4d 63 e4             	movsxd r12,r12d
  2c:	4d 63 e4             	movsxd r12,r12d
  2f:	4d 63 e4             	movsxd r12,r12d
  32:	4d 63 e4             	movsxd r12,r12d
  35:	4d 63 e4             	movsxd r12,r12d
  38:	4d 63 e4             	movsxd r12,r12d
  3b:	4d 63 e4             	movsxd r12,r12d
  3e:	4d 63 e4             	movsxd r12,r12d
  41:	4d 63 e4             	movsxd r12,r12d
  44:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 23.0
- Core cycles: 37.0
- Reference cycles: 38.24
- UOPS_RETIRED.ALL: 23.0

Experiment 3

Instruction: LOCK INC dword ptr [R14]
Chain instructions: CMOVP R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥22

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	4d 0f 4a e4          	cmovp  r12,r12
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	4d 63 e4             	movsxd r12,r12d
  29:	4d 63 e4             	movsxd r12,r12d
  2c:	4d 63 e4             	movsxd r12,r12d
  2f:	4d 63 e4             	movsxd r12,r12d
  32:	4d 63 e4             	movsxd r12,r12d
  35:	4d 63 e4             	movsxd r12,r12d
  38:	4d 63 e4             	movsxd r12,r12d
  3b:	4d 63 e4             	movsxd r12,r12d
  3e:	4d 63 e4             	movsxd r12,r12d
  41:	4d 63 e4             	movsxd r12,r12d
  44:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 23.0
- Core cycles: 37.0
- Reference cycles: 37.92
- UOPS_RETIRED.ALL: 23.0

Experiment 4

Instruction: LOCK INC dword ptr [R14]
Chain instructions: CMOVZ R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12D
Chain latency: ≥22

Code:

   0:	f0 41 ff 06          	lock inc DWORD PTR [r14]
   4:	4d 0f 44 e4          	cmove  r12,r12
   8:	4d 63 e4             	movsxd r12,r12d
   b:	4d 63 e4             	movsxd r12,r12d
   e:	4d 63 e4             	movsxd r12,r12d
  11:	4d 63 e4             	movsxd r12,r12d
  14:	4d 63 e4             	movsxd r12,r12d
  17:	4d 63 e4             	movsxd r12,r12d
  1a:	4d 63 e4             	movsxd r12,r12d
  1d:	4d 63 e4             	movsxd r12,r12d
  20:	4d 63 e4             	movsxd r12,r12d
  23:	4d 63 e4             	movsxd r12,r12d
  26:	4d 63 e4             	movsxd r12,r12d
  29:	4d 63 e4             	movsxd r12,r12d
  2c:	4d 63 e4             	movsxd r12,r12d
  2f:	4d 63 e4             	movsxd r12,r12d
  32:	4d 63 e4             	movsxd r12,r12d
  35:	4d 63 e4             	movsxd r12,r12d
  38:	4d 63 e4             	movsxd r12,r12d
  3b:	4d 63 e4             	movsxd r12,r12d
  3e:	4d 63 e4             	movsxd r12,r12d
  41:	4d 63 e4             	movsxd r12,r12d
  44:	45 89 26             	mov    DWORD PTR [r14],r12d

Show nanoBench command
Results:
- Instructions retired: 23.0
- Core cycles: 37.0
- Reference cycles: 38.24
- UOPS_RETIRED.ALL: 23.0

INC_LOCK (M32) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤21

Latency operand 1 → 1 (address, index register): ≤21

Latency operand 1 → 1 (memory): 18

Latency operand 1 → 2 (address, base register): 16

Latency operand 1 → 2 (address, index register): 16

Latency operand 1 → 2 (memory): ≤15

Latency operand 1 → 1 (address, base register): ≤21

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤21

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (memory): 18

Experiment 1

Experiment 2

Latency operand 1 → 2 (address, base register): 16

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7

Experiment 8 (with dependency-breaking instructions)

Latency operand 1 → 2 (address, index register): 16

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7

Experiment 8 (with dependency-breaking instructions)

Latency operand 1 → 2 (memory): ≤15

Experiment 1

Experiment 2

Experiment 3

Experiment 4