DIV (M64) - Latency


Operands


Latency operand 1 → 2 (address, base register): 15 ≤ lat ≤ 46

Latency operand 1 → 2 (address, index register): 15 ≤ lat ≤ 46

Latency operand 1 → 3 (address, base register): 16 ≤ lat ≤ 47

Latency operand 1 → 3 (address, index register): 16 ≤ lat ≤ 47

Latency operand 2 → 2: 11 ≤ lat ≤ 42

Latency operand 2 → 3: 12 ≤ lat ≤ 43

Latency operand 3 → 2: 11 ≤ lat ≤ 42

Latency operand 3 → 3: 11 ≤ lat ≤ 42


Latency operand 1 → 2 (address, base register): 15 ≤ lat ≤ 46

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 2 (address, index register): 15 ≤ lat ≤ 46

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, base register): 16 ≤ lat ≤ 47

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 1 → 3 (address, index register): 16 ≤ lat ≤ 47

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 2: 11 ≤ lat ≤ 42

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 2 → 3: 12 ≤ lat ≤ 43

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 2: 11 ≤ lat ≤ 42

Experiment 1 (fast division)

Experiment 2 (slow division)


Latency operand 3 → 3: 11 ≤ lat ≤ 42

Experiment 1 (fast division)

Experiment 2 (slow division)