ADD (M8, I8) - Latency


Operands


Latency operand 1 → 1 (address, base register): ≤5

Latency operand 1 → 1 (address, index register): ≤4

Latency operand 1 → 1 (memory): 1

Latency operand 1 → 3 (address, base register): 0

Latency operand 1 → 3 (address, index register): 0

Latency operand 1 → 3 (memory): ≤1


Latency operand 1 → 1 (address, base register): ≤5

Experiment 1

Experiment 2 (with additional nop)


Latency operand 1 → 1 (address, index register): ≤4

Experiment 1

Experiment 2 (with additional nop)


Latency operand 1 → 1 (memory): 1

Experiment 1

Experiment 2


Latency operand 1 → 3 (address, base register): 0

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5


Latency operand 1 → 3 (address, index register): 0

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5


Latency operand 1 → 3 (memory): ≤1

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5