ADC_LOCK (M16, I8)

Experiment 1

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: MOV R12W, [R14];MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;XOR R14, R12; XOR R14, R12;TEST R15, R15
Chain latency: ≥22

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	66 45 8b 26          	mov    r12w,WORD PTR [r14]
   a:	4d 0f bf e4          	movsx  r12,r12w
   e:	4d 0f bf e4          	movsx  r12,r12w
  12:	4d 0f bf e4          	movsx  r12,r12w
  16:	4d 0f bf e4          	movsx  r12,r12w
  1a:	4d 0f bf e4          	movsx  r12,r12w
  1e:	4d 0f bf e4          	movsx  r12,r12w
  22:	4d 0f bf e4          	movsx  r12,r12w
  26:	4d 0f bf e4          	movsx  r12,r12w
  2a:	4d 0f bf e4          	movsx  r12,r12w
  2e:	4d 0f bf e4          	movsx  r12,r12w
  32:	4d 0f bf e4          	movsx  r12,r12w
  36:	4d 0f bf e4          	movsx  r12,r12w
  3a:	4d 0f bf e4          	movsx  r12,r12w
  3e:	4d 0f bf e4          	movsx  r12,r12w
  42:	4d 0f bf e4          	movsx  r12,r12w
  46:	4d 0f bf e4          	movsx  r12,r12w
  4a:	4d 0f bf e4          	movsx  r12,r12w
  4e:	4d 0f bf e4          	movsx  r12,r12w
  52:	4d 0f bf e4          	movsx  r12,r12w
  56:	4d 0f bf e4          	movsx  r12,r12w
  5a:	4d 31 e6             	xor    r14,r12
  5d:	4d 31 e6             	xor    r14,r12
  60:	4d 85 ff             	test   r15,r15

Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 43.83
- Reference cycles: 44.8
- UOPS_RETIRED.ALL: 25.0

Experiment 2 (with additional nop)

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: MOV R12W, [R14];MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;XOR R14, R12; XOR R14, R12;TEST R15, R15;nop
Chain latency: ≥22

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	66 45 8b 26          	mov    r12w,WORD PTR [r14]
   a:	4d 0f bf e4          	movsx  r12,r12w
   e:	4d 0f bf e4          	movsx  r12,r12w
  12:	4d 0f bf e4          	movsx  r12,r12w
  16:	4d 0f bf e4          	movsx  r12,r12w
  1a:	4d 0f bf e4          	movsx  r12,r12w
  1e:	4d 0f bf e4          	movsx  r12,r12w
  22:	4d 0f bf e4          	movsx  r12,r12w
  26:	4d 0f bf e4          	movsx  r12,r12w
  2a:	4d 0f bf e4          	movsx  r12,r12w
  2e:	4d 0f bf e4          	movsx  r12,r12w
  32:	4d 0f bf e4          	movsx  r12,r12w
  36:	4d 0f bf e4          	movsx  r12,r12w
  3a:	4d 0f bf e4          	movsx  r12,r12w
  3e:	4d 0f bf e4          	movsx  r12,r12w
  42:	4d 0f bf e4          	movsx  r12,r12w
  46:	4d 0f bf e4          	movsx  r12,r12w
  4a:	4d 0f bf e4          	movsx  r12,r12w
  4e:	4d 0f bf e4          	movsx  r12,r12w
  52:	4d 0f bf e4          	movsx  r12,r12w
  56:	4d 0f bf e4          	movsx  r12,r12w
  5a:	4d 31 e6             	xor    r14,r12
  5d:	4d 31 e6             	xor    r14,r12
  60:	4d 85 ff             	test   r15,r15
  63:	90                   	nop

Show nanoBench command
Results:
- Instructions retired: 26.0
- Core cycles: 43.84
- Reference cycles: 44.64
- UOPS_RETIRED.ALL: 26.0

Latency operand 1 → 1 (address, index register): ≤22

Experiment 1

Instruction: LOCK ADC word ptr [R14+R13], 2
Chain instructions: MOV R12W, [R14+R13];MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;XOR R13, R12; XOR R13, R12;TEST R15, R15
Chain latency: ≥22

Code:

   0:	66 f0 43 83 14 2e 02 	lock adc WORD PTR [r14+r13*1],0x2
   7:	66 47 8b 24 2e       	mov    r12w,WORD PTR [r14+r13*1]
   c:	4d 0f bf e4          	movsx  r12,r12w
  10:	4d 0f bf e4          	movsx  r12,r12w
  14:	4d 0f bf e4          	movsx  r12,r12w
  18:	4d 0f bf e4          	movsx  r12,r12w
  1c:	4d 0f bf e4          	movsx  r12,r12w
  20:	4d 0f bf e4          	movsx  r12,r12w
  24:	4d 0f bf e4          	movsx  r12,r12w
  28:	4d 0f bf e4          	movsx  r12,r12w
  2c:	4d 0f bf e4          	movsx  r12,r12w
  30:	4d 0f bf e4          	movsx  r12,r12w
  34:	4d 0f bf e4          	movsx  r12,r12w
  38:	4d 0f bf e4          	movsx  r12,r12w
  3c:	4d 0f bf e4          	movsx  r12,r12w
  40:	4d 0f bf e4          	movsx  r12,r12w
  44:	4d 0f bf e4          	movsx  r12,r12w
  48:	4d 0f bf e4          	movsx  r12,r12w
  4c:	4d 0f bf e4          	movsx  r12,r12w
  50:	4d 0f bf e4          	movsx  r12,r12w
  54:	4d 0f bf e4          	movsx  r12,r12w
  58:	4d 0f bf e4          	movsx  r12,r12w
  5c:	4d 31 e5             	xor    r13,r12
  5f:	4d 31 e5             	xor    r13,r12
  62:	4d 85 ff             	test   r15,r15

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 25.0
- Core cycles: 43.83
- Reference cycles: 44.8
- UOPS_RETIRED.ALL: 25.0

Experiment 2 (with additional nop)

Instruction: LOCK ADC word ptr [R14+R13], 2
Chain instructions: MOV R12W, [R14+R13];MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;XOR R13, R12; XOR R13, R12;TEST R15, R15;nop
Chain latency: ≥22

Code:

   0:	66 f0 43 83 14 2e 02 	lock adc WORD PTR [r14+r13*1],0x2
   7:	66 47 8b 24 2e       	mov    r12w,WORD PTR [r14+r13*1]
   c:	4d 0f bf e4          	movsx  r12,r12w
  10:	4d 0f bf e4          	movsx  r12,r12w
  14:	4d 0f bf e4          	movsx  r12,r12w
  18:	4d 0f bf e4          	movsx  r12,r12w
  1c:	4d 0f bf e4          	movsx  r12,r12w
  20:	4d 0f bf e4          	movsx  r12,r12w
  24:	4d 0f bf e4          	movsx  r12,r12w
  28:	4d 0f bf e4          	movsx  r12,r12w
  2c:	4d 0f bf e4          	movsx  r12,r12w
  30:	4d 0f bf e4          	movsx  r12,r12w
  34:	4d 0f bf e4          	movsx  r12,r12w
  38:	4d 0f bf e4          	movsx  r12,r12w
  3c:	4d 0f bf e4          	movsx  r12,r12w
  40:	4d 0f bf e4          	movsx  r12,r12w
  44:	4d 0f bf e4          	movsx  r12,r12w
  48:	4d 0f bf e4          	movsx  r12,r12w
  4c:	4d 0f bf e4          	movsx  r12,r12w
  50:	4d 0f bf e4          	movsx  r12,r12w
  54:	4d 0f bf e4          	movsx  r12,r12w
  58:	4d 0f bf e4          	movsx  r12,r12w
  5c:	4d 31 e5             	xor    r13,r12
  5f:	4d 31 e5             	xor    r13,r12
  62:	4d 85 ff             	test   r15,r15
  65:	90                   	nop

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 26.0
- Core cycles: 43.84
- Reference cycles: 44.64
- UOPS_RETIRED.ALL: 26.0

Latency operand 1 → 1 (memory): 18

Experiment 1

Instruction: LOCK ADC word ptr [R14], 2

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 17.97
- Reference cycles: 18.56
- UOPS_RETIRED.ALL: 1.0

Experiment 2 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14], 2
Chain instruction: TEST R15, R15

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 85 ff             	test   r15,r15

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 17.97
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 2.0

Experiment 3

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: MOV R12W, [R14];MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOV [R14], R12W
Chain latency: 11

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	66 45 8b 26          	mov    r12w,WORD PTR [r14]
   a:	4d 0f bf e4          	movsx  r12,r12w
   e:	4d 0f bf e4          	movsx  r12,r12w
  12:	4d 0f bf e4          	movsx  r12,r12w
  16:	4d 0f bf e4          	movsx  r12,r12w
  1a:	4d 0f bf e4          	movsx  r12,r12w
  1e:	4d 0f bf e4          	movsx  r12,r12w
  22:	4d 0f bf e4          	movsx  r12,r12w
  26:	4d 0f bf e4          	movsx  r12,r12w
  2a:	4d 0f bf e4          	movsx  r12,r12w
  2e:	4d 0f bf e4          	movsx  r12,r12w
  32:	66 45 89 26          	mov    WORD PTR [r14],r12w

Show nanoBench command
Results:
- Instructions retired: 13.0
- Core cycles: 31.32
- Reference cycles: 32.16
- UOPS_RETIRED.ALL: 13.0

Experiment 4 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: MOV R12W, [R14];MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOVSX R12, R12W;MOV [R14], R12W;TEST R15, R15
Chain latency: 11

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	66 45 8b 26          	mov    r12w,WORD PTR [r14]
   a:	4d 0f bf e4          	movsx  r12,r12w
   e:	4d 0f bf e4          	movsx  r12,r12w
  12:	4d 0f bf e4          	movsx  r12,r12w
  16:	4d 0f bf e4          	movsx  r12,r12w
  1a:	4d 0f bf e4          	movsx  r12,r12w
  1e:	4d 0f bf e4          	movsx  r12,r12w
  22:	4d 0f bf e4          	movsx  r12,r12w
  26:	4d 0f bf e4          	movsx  r12,r12w
  2a:	4d 0f bf e4          	movsx  r12,r12w
  2e:	4d 0f bf e4          	movsx  r12,r12w
  32:	66 45 89 26          	mov    WORD PTR [r14],r12w
  36:	4d 85 ff             	test   r15,r15

Show nanoBench command
Results:
- Instructions retired: 14.0
- Core cycles: 31.32
- Reference cycles: 32.0
- UOPS_RETIRED.ALL: 14.0

Latency operand 1 → 3 (address, base register): 16

Experiment 1

Instruction: LOCK ADC word ptr [R14], 2
Chain instruction: CMOVC R14, R14
Chain latency: 2

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 42 f6          	cmovb  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 2.0

Experiment 2 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: CMOVC R14, R14;TEST R15, R15
Chain latency: 2

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 42 f6          	cmovb  r14,r14
   a:	4d 85 ff             	test   r15,r15

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 3.0

Experiment 3

Instruction: LOCK ADC word ptr [R14], 2
Chain instruction: CMOVS R14, R14
Chain latency: 2

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 48 f6          	cmovs  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 2.0

Experiment 4 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: CMOVS R14, R14;TEST R15, R15
Chain latency: 2

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 48 f6          	cmovs  r14,r14
   a:	4d 85 ff             	test   r15,r15

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 3.0

Experiment 5

Instruction: LOCK ADC word ptr [R14], 2
Chain instruction: CMOVO R14, R14
Chain latency: 2

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 40 f6          	cmovo  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 2.0

Experiment 6 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: CMOVO R14, R14;TEST R15, R15
Chain latency: 2

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 40 f6          	cmovo  r14,r14
   a:	4d 85 ff             	test   r15,r15

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 3.0

Experiment 7

Instruction: LOCK ADC word ptr [R14], 2
Chain instruction: CMOVP R14, R14
Chain latency: 2

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 4a f6          	cmovp  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 2.0

Experiment 8 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: CMOVP R14, R14;TEST R15, R15
Chain latency: 2

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 4a f6          	cmovp  r14,r14
   a:	4d 85 ff             	test   r15,r15

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 3.0

Experiment 9

Instruction: LOCK ADC word ptr [R14], 2
Chain instruction: CMOVZ R14, R14
Chain latency: 2

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 44 f6          	cmove  r14,r14

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 2.0

Experiment 10 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: CMOVZ R14, R14;TEST R15, R15
Chain latency: 2

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 44 f6          	cmove  r14,r14
   a:	4d 85 ff             	test   r15,r15

Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 3.0

Latency operand 1 → 3 (address, index register): 16

Experiment 1

Instruction: LOCK ADC word ptr [R14+R13], 2
Chain instruction: CMOVC R13, R13
Chain latency: 2

Code:

   0:	66 f0 43 83 14 2e 02 	lock adc WORD PTR [r14+r13*1],0x2
   7:	4d 0f 42 ed          	cmovb  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 2.0

Experiment 2 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14+R13], 2
Chain instructions: CMOVC R13, R13;TEST R15, R15
Chain latency: 2

Code:

   0:	66 f0 43 83 14 2e 02 	lock adc WORD PTR [r14+r13*1],0x2
   7:	4d 0f 42 ed          	cmovb  r13,r13
   b:	4d 85 ff             	test   r15,r15

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 3.0

Experiment 3

Instruction: LOCK ADC word ptr [R14+R13], 2
Chain instruction: CMOVS R13, R13
Chain latency: 2

Code:

   0:	66 f0 43 83 14 2e 02 	lock adc WORD PTR [r14+r13*1],0x2
   7:	4d 0f 48 ed          	cmovs  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 2.0

Experiment 4 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14+R13], 2
Chain instructions: CMOVS R13, R13;TEST R15, R15
Chain latency: 2

Code:

   0:	66 f0 43 83 14 2e 02 	lock adc WORD PTR [r14+r13*1],0x2
   7:	4d 0f 48 ed          	cmovs  r13,r13
   b:	4d 85 ff             	test   r15,r15

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 3.0

Experiment 5

Instruction: LOCK ADC word ptr [R14+R13], 2
Chain instruction: CMOVO R13, R13
Chain latency: 2

Code:

   0:	66 f0 43 83 14 2e 02 	lock adc WORD PTR [r14+r13*1],0x2
   7:	4d 0f 40 ed          	cmovo  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 2.0

Experiment 6 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14+R13], 2
Chain instructions: CMOVO R13, R13;TEST R15, R15
Chain latency: 2

Code:

   0:	66 f0 43 83 14 2e 02 	lock adc WORD PTR [r14+r13*1],0x2
   7:	4d 0f 40 ed          	cmovo  r13,r13
   b:	4d 85 ff             	test   r15,r15

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 3.0

Experiment 7

Instruction: LOCK ADC word ptr [R14+R13], 2
Chain instruction: CMOVP R13, R13
Chain latency: 2

Code:

   0:	66 f0 43 83 14 2e 02 	lock adc WORD PTR [r14+r13*1],0x2
   7:	4d 0f 4a ed          	cmovp  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 2.0

Experiment 8 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14+R13], 2
Chain instructions: CMOVP R13, R13;TEST R15, R15
Chain latency: 2

Code:

   0:	66 f0 43 83 14 2e 02 	lock adc WORD PTR [r14+r13*1],0x2
   7:	4d 0f 4a ed          	cmovp  r13,r13
   b:	4d 85 ff             	test   r15,r15

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 3.0

Experiment 9

Instruction: LOCK ADC word ptr [R14+R13], 2
Chain instruction: CMOVZ R13, R13
Chain latency: 2

Code:

   0:	66 f0 43 83 14 2e 02 	lock adc WORD PTR [r14+r13*1],0x2
   7:	4d 0f 44 ed          	cmove  r13,r13

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 18.0
- Reference cycles: 18.56
- UOPS_RETIRED.ALL: 2.0

Experiment 10 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14+R13], 2
Chain instructions: CMOVZ R13, R13;TEST R15, R15
Chain latency: 2

Code:

   0:	66 f0 43 83 14 2e 02 	lock adc WORD PTR [r14+r13*1],0x2
   7:	4d 0f 44 ed          	cmove  r13,r13
   b:	4d 85 ff             	test   r15,r15

Init:
```
XOR R13, R13
```
Show nanoBench command
Results:
- Instructions retired: 3.0
- Core cycles: 18.0
- Reference cycles: 18.24
- UOPS_RETIRED.ALL: 3.0

Latency operand 1 → 3 (memory): ≤14

Experiment 1

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: CMOVC R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12W
Chain latency: ≥22

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 42 e4          	cmovb  r12,r12
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	4d 63 e4             	movsxd r12,r12d
  28:	4d 63 e4             	movsxd r12,r12d
  2b:	4d 63 e4             	movsxd r12,r12d
  2e:	4d 63 e4             	movsxd r12,r12d
  31:	4d 63 e4             	movsxd r12,r12d
  34:	4d 63 e4             	movsxd r12,r12d
  37:	4d 63 e4             	movsxd r12,r12d
  3a:	4d 63 e4             	movsxd r12,r12d
  3d:	4d 63 e4             	movsxd r12,r12d
  40:	4d 63 e4             	movsxd r12,r12d
  43:	4d 63 e4             	movsxd r12,r12d
  46:	66 45 89 26          	mov    WORD PTR [r14],r12w

Show nanoBench command
Results:
- Instructions retired: 23.0
- Core cycles: 36.0
- Reference cycles: 36.96
- UOPS_RETIRED.ALL: 23.0

Experiment 2

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: CMOVS R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12W
Chain latency: ≥22

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 48 e4          	cmovs  r12,r12
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	4d 63 e4             	movsxd r12,r12d
  28:	4d 63 e4             	movsxd r12,r12d
  2b:	4d 63 e4             	movsxd r12,r12d
  2e:	4d 63 e4             	movsxd r12,r12d
  31:	4d 63 e4             	movsxd r12,r12d
  34:	4d 63 e4             	movsxd r12,r12d
  37:	4d 63 e4             	movsxd r12,r12d
  3a:	4d 63 e4             	movsxd r12,r12d
  3d:	4d 63 e4             	movsxd r12,r12d
  40:	4d 63 e4             	movsxd r12,r12d
  43:	4d 63 e4             	movsxd r12,r12d
  46:	66 45 89 26          	mov    WORD PTR [r14],r12w

Show nanoBench command
Results:
- Instructions retired: 23.0
- Core cycles: 36.0
- Reference cycles: 37.12
- UOPS_RETIRED.ALL: 23.0

Experiment 3

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: CMOVO R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12W
Chain latency: ≥22

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 40 e4          	cmovo  r12,r12
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	4d 63 e4             	movsxd r12,r12d
  28:	4d 63 e4             	movsxd r12,r12d
  2b:	4d 63 e4             	movsxd r12,r12d
  2e:	4d 63 e4             	movsxd r12,r12d
  31:	4d 63 e4             	movsxd r12,r12d
  34:	4d 63 e4             	movsxd r12,r12d
  37:	4d 63 e4             	movsxd r12,r12d
  3a:	4d 63 e4             	movsxd r12,r12d
  3d:	4d 63 e4             	movsxd r12,r12d
  40:	4d 63 e4             	movsxd r12,r12d
  43:	4d 63 e4             	movsxd r12,r12d
  46:	66 45 89 26          	mov    WORD PTR [r14],r12w

Show nanoBench command
Results:
- Instructions retired: 23.0
- Core cycles: 36.0
- Reference cycles: 37.12
- UOPS_RETIRED.ALL: 23.0

Experiment 4

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: CMOVP R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12W
Chain latency: ≥22

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 4a e4          	cmovp  r12,r12
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	4d 63 e4             	movsxd r12,r12d
  28:	4d 63 e4             	movsxd r12,r12d
  2b:	4d 63 e4             	movsxd r12,r12d
  2e:	4d 63 e4             	movsxd r12,r12d
  31:	4d 63 e4             	movsxd r12,r12d
  34:	4d 63 e4             	movsxd r12,r12d
  37:	4d 63 e4             	movsxd r12,r12d
  3a:	4d 63 e4             	movsxd r12,r12d
  3d:	4d 63 e4             	movsxd r12,r12d
  40:	4d 63 e4             	movsxd r12,r12d
  43:	4d 63 e4             	movsxd r12,r12d
  46:	66 45 89 26          	mov    WORD PTR [r14],r12w

Show nanoBench command
Results:
- Instructions retired: 23.0
- Core cycles: 36.0
- Reference cycles: 36.96
- UOPS_RETIRED.ALL: 23.0

Experiment 5

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: CMOVZ R12, R12;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;MOVSX R12, R12d;mov [R14], R12W
Chain latency: ≥22

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	4d 0f 44 e4          	cmove  r12,r12
   a:	4d 63 e4             	movsxd r12,r12d
   d:	4d 63 e4             	movsxd r12,r12d
  10:	4d 63 e4             	movsxd r12,r12d
  13:	4d 63 e4             	movsxd r12,r12d
  16:	4d 63 e4             	movsxd r12,r12d
  19:	4d 63 e4             	movsxd r12,r12d
  1c:	4d 63 e4             	movsxd r12,r12d
  1f:	4d 63 e4             	movsxd r12,r12d
  22:	4d 63 e4             	movsxd r12,r12d
  25:	4d 63 e4             	movsxd r12,r12d
  28:	4d 63 e4             	movsxd r12,r12d
  2b:	4d 63 e4             	movsxd r12,r12d
  2e:	4d 63 e4             	movsxd r12,r12d
  31:	4d 63 e4             	movsxd r12,r12d
  34:	4d 63 e4             	movsxd r12,r12d
  37:	4d 63 e4             	movsxd r12,r12d
  3a:	4d 63 e4             	movsxd r12,r12d
  3d:	4d 63 e4             	movsxd r12,r12d
  40:	4d 63 e4             	movsxd r12,r12d
  43:	4d 63 e4             	movsxd r12,r12d
  46:	66 45 89 26          	mov    WORD PTR [r14],r12w

Show nanoBench command
Results:
- Instructions retired: 23.0
- Core cycles: 36.0
- Reference cycles: 36.8
- UOPS_RETIRED.ALL: 23.0

Latency operand 3 → 1: ≤18

Latency operand 3 → 3: 12

Experiment 1

Instruction: LOCK ADC word ptr [R14], 2
Chain instructions: CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC;CMC
Chain latency: 20

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	f5                   	cmc    
   7:	f5                   	cmc    
   8:	f5                   	cmc    
   9:	f5                   	cmc    
   a:	f5                   	cmc    
   b:	f5                   	cmc    
   c:	f5                   	cmc    
   d:	f5                   	cmc    
   e:	f5                   	cmc    
   f:	f5                   	cmc    
  10:	f5                   	cmc    
  11:	f5                   	cmc    
  12:	f5                   	cmc    
  13:	f5                   	cmc    
  14:	f5                   	cmc    
  15:	f5                   	cmc    
  16:	f5                   	cmc    
  17:	f5                   	cmc    
  18:	f5                   	cmc    
  19:	f5                   	cmc

Show nanoBench command
Results:
- Instructions retired: 21.0
- Core cycles: 32.25
- Reference cycles: 32.8
- UOPS_RETIRED.ALL: 21.0

Experiment 2

Instruction: LOCK ADC word ptr [R14], 2

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2

Show nanoBench command
Results:
- Instructions retired: 1.0
- Core cycles: 18.0
- Reference cycles: 18.4
- UOPS_RETIRED.ALL: 1.0

Experiment 3 (with dependency-breaking instructions)

Instruction: LOCK ADC word ptr [R14], 2
Chain instruction: MOV word ptr [R14], 0

Code:

   0:	66 f0 41 83 16 02    	lock adc WORD PTR [r14],0x2
   6:	66 41 c7 06 00 00    	mov    WORD PTR [r14],0x0

Show nanoBench command
Results:
- Instructions retired: 2.0
- Core cycles: 19.0
- Reference cycles: 19.52
- UOPS_RETIRED.ALL: 2.0

ADC_LOCK (M16, I8) - Latency

Operands

Latency operand 1 → 1 (address, base register): ≤22

Latency operand 1 → 1 (address, index register): ≤22

Latency operand 1 → 1 (memory): 18

Latency operand 1 → 3 (address, base register): 16

Latency operand 1 → 3 (address, index register): 16

Latency operand 1 → 3 (memory): ≤14

Latency operand 3 → 1: ≤18

Latency operand 3 → 3: 12

Latency operand 1 → 1 (address, base register): ≤22

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (address, index register): ≤22

Experiment 1

Experiment 2 (with additional nop)

Latency operand 1 → 1 (memory): 18

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Latency operand 1 → 3 (address, base register): 16

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7

Experiment 8 (with dependency-breaking instructions)

Experiment 9

Experiment 10 (with dependency-breaking instructions)

Latency operand 1 → 3 (address, index register): 16

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Experiment 3

Experiment 4 (with dependency-breaking instructions)

Experiment 5

Experiment 6 (with dependency-breaking instructions)

Experiment 7

Experiment 8 (with dependency-breaking instructions)

Experiment 9

Experiment 10 (with dependency-breaking instructions)

Latency operand 1 → 3 (memory): ≤14

Experiment 1

Experiment 2

Experiment 3

Experiment 4

Experiment 5

Latency operand 3 → 1: ≤18

Experiment 1

Experiment 2 (with dependency-breaking instructions)

Latency operand 3 → 3: 12

Experiment 1

Experiment 2

Experiment 3 (with dependency-breaking instructions)