VSCATTERQPD (VSIB_ZMM, K, ZMM)

Operands

• Operand 1 (w): Memory
• Operand 2 (r/w): Register (K1, K2, K3, K4, K5, K6, K7)
• Operand 3 (r): Register (ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15, ZMM16, ZMM17, ZMM18, ZMM19, ZMM20, ZMM21, ZMM22, ZMM23, ZMM24, ZMM25, ZMM26, ZMM27, ZMM28, ZMM29, ZMM30, ZMM31)

Available performance data

• Alder Lake-P
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• AMD Zen 4

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤12
  • Latency operand 2 → 2: 2
  • Latency operand 3 → 1: ≤6
  • Latency operand 3 → 2: 7
• Throughput
  • Computed from the port usage: 4.00
  • Measured (loop): 7.00
  • Measured (unrolled): 7.00
• Number of μops
  • Executed: 19
  • Retire slots: 20
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 16
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0+1*p0156B+8*p49+8*p78

Rocket Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤16
  • Latency operand 2 → 2: 2
  • Latency operand 3 → 1: ≤6
  • Latency operand 3 → 2: 7
• Throughput
  • Computed from the port usage: 4.00
  • Measured (loop): 7.00
  • Measured (unrolled): 7.00
• Number of μops
  • Executed: 19
  • Retire slots: 20
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 16
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0+1*p015+8*p49+8*p78

Tiger Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤16
  • Latency operand 2 → 2: 2
  • Latency operand 3 → 1: ≤6
  • Latency operand 3 → 2: 7
• Throughput
  • Computed from the port usage: 4.00
  • Measured (loop): 7.00
  • Measured (unrolled): 7.00
• Number of μops
  • Executed: 19
  • Retire slots: 20
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 16
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0+1*p015+8*p49+8*p78

Ice Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤16
  • Latency operand 2 → 2: 2
  • Latency operand 3 → 1: ≤6
  • Latency operand 3 → 2: 7
• Throughput
  • Computed from the port usage: 4.00
  • Measured (loop): 7.00
  • Measured (unrolled): 7.00
• Number of μops
  • Executed: 19
  • Retire slots: 20
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 16
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0+1*p015+8*p49+8*p78

Cascade Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤15
  • Latency operand 2 → 2: 2
  • Latency operand 3 → 1: ≤7
  • Latency operand 3 → 2: 8
• Throughput
  • Computed from the port usage: 8.00
  • Measured (loop): 9.00
  • Measured (unrolled): 9.00
• Number of μops
  • Executed: 19
  • Retire slots: 20
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 16
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0+8*p23+8*p4

Cannon Lake

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤15
  • Latency operand 2 → 2: 2
  • Latency operand 3 → 1: ≤7
  • Latency operand 3 → 2: 8
• Throughput
  • Computed from the port usage: 8.00
  • Measured (loop): 9.00
  • Measured (unrolled): 9.00
• Number of μops
  • Executed: 19
  • Retire slots: 20
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 16
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0+8*p23+8*p4

Skylake-X

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤15
  • Latency operand 2 → 2: 2
  • Latency operand 3 → 1: ≤7
  • Latency operand 3 → 2: 8
• Throughput
  • Computed from the port usage: 8.00
  • Measured (loop): 9.00
  • Measured (unrolled): 9.00
• Number of μops
  • Executed: 19
  • Retire slots: 20
  • Decoded (MITE): 4
  • Microcode Sequencer (MS): 16
  • Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
• Port usage: 2*p0+8*p23+8*p4
• IACA 2.3
• Throughput
  • Computed from the port usage: 8.00
  • IACA: 8.00
• Number of μops: 19
• Port usage: 1*p0+2*p0156+8*p23+8*p4
• IACA 3.0
• Throughput
  • Computed from the port usage: 8.00
  • IACA: 8.00
• Number of μops: 19
• Port usage: 1*p0+2*p0156+8*p23+8*p4

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 1 → 1 (address, base register): ≤42
  • Latency operand 2 → 2: 1
  • Latency operand 3 → 1: ≤13
  • Latency operand 3 → 2: 11
• Throughput
  • Computed from the port usage: 9.00
  • Measured (loop): 12.15
  • Measured (unrolled): 12.08
• Number of μops
  • Executed: 48
• Port usage: 4*FP12+1*FP123+3*FP23+18*FP45