VPMOVZXBD (YMM, M64)

Operands

• Operand 1 (w): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)
• Operand 2 (r): Memory

Available performance data

• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00 (if an indexed addressing mode is used: 0.33)
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (4 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23A+1*p5 (if an indexed addressing mode is used: 1*p23A)

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Measured (loop): 0.67
  • Measured (unrolled): 0.65
• Number of μops
  • Executed: 2
  • Microcode Sequencer (MS): 0

Rocket Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5

Tiger Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5

Ice Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5
• Documentation
• Throughput: 1.0

Cascade Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5

Cannon Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5

Skylake-X

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5

Coffee Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5

Kaby Lake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5

Skylake

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (3 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5

Broadwell

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤10
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5

Haswell

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤11
  • Latency operand 2 → 1 (address, index register): ≤11
  • Latency operand 2 → 1 (memory): ≤10
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 2
  • Decoded (MITE): 2
  • Microcode Sequencer (MS): 0
  • Requires the complex decoder (2 other instructions can be decoded with simple decoders in the same cycle)
• Port usage: 1*p23+1*p5
• IACA 2.1
• Latency: 10
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5
• IACA 3.0
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p23+1*p5

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤10
  • Latency operand 2 → 1 (address, index register): ≤10
  • Latency operand 2 → 1 (memory): ≤10
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP12

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤9
  • Latency operand 2 → 1 (address, index register): ≤9
  • Latency operand 2 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP12

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤9
  • Latency operand 2 → 1 (address, index register): ≤9
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP12

AMD Zen+

• Measurements
• Latencies
  • Latency operand 2 → 1 (address, base register): ≤10
  • Latency operand 2 → 1 (address, index register): ≤10
  • Latency operand 2 → 1 (memory): ≤8
• Throughput
  • Measured (loop): 2.00
  • Measured (unrolled): 2.00
• Number of μops
  • Executed: 4