VP2INTERSECTD (R64, YMM, YMM)

Summary:	"Compute Intersection Between DWORDS/QUADWORDS to a Pair of Mask Registers"
Reference:	https://www.felixcloutier.com/x86/VP2INTERSECTD:VP2INTERSECTQ.html
Extension:	AVX512EVEX
Category:	AVX512_VP2INTERSECT
ISA-Set:	AVX512_VP2INTERSECT_256
CPL:	3
iform:	VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512
iclass:	VP2INTERSECTD
ASM:	VP2INTERSECTD

Operands

Operand 1 (w): Register (K0, K2, K4, K6)
Operand 2 (r): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15, YMM16, YMM17, YMM18, YMM19, YMM20, YMM21, YMM22, YMM23, YMM24, YMM25, YMM26, YMM27, YMM28, YMM29, YMM30, YMM31)
Operand 3 (r): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15, YMM16, YMM17, YMM18, YMM19, YMM20, YMM21, YMM22, YMM23, YMM24, YMM25, YMM26, YMM27, YMM28, YMM29, YMM30, YMM31)

Latencies
- Latency operand 2 → 1: 27
- Latency operand 3 → 1: 26
Throughput
- Computed from the port usage: 11.00
- Measured (loop): 11.50
- Measured (unrolled): 11.64
Number of μops
- Executed: 30
- Retire slots: 30
- Decoded (MITE): 4
- Microcode Sequencer (MS): 26
- Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+8*p01+8*p015+2*p15+11*p5

Latencies
- Latency operand 2 → 1: 27
- Latency operand 3 → 1: 25
Throughput
- Computed from the port usage: 11.00
- Measured (loop): 11.91
- Measured (unrolled): 11.86
Number of μops
- Executed: 30
- Retire slots: 30
- Decoded (MITE): 4
- Microcode Sequencer (MS): 26
- Requires the complex decoder (no other instruction can be decoded with simple decoders in the same cycle)
Port usage: 1*p0+8*p01+8*p015+2*p15+11*p5