VMULPS (YMM, YMM, M256)

Operands

• Operand 1 (w): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)
• Operand 2 (r): Register (YMM0, YMM1, YMM2, YMM3, YMM4, YMM5, YMM6, YMM7, YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15)
• Operand 3 (r): Memory

Available performance data

• Alder Lake-P
• Alder Lake-E
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• Coffee Lake
• Kaby Lake
• Skylake
• Broadwell
• Haswell
• Ivy Bridge
• Sandy Bridge
• AMD Zen 4
• AMD Zen 3
• AMD Zen 2
• AMD Zen+

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50 (if an indexed addressing mode is used: 0.52)
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p01+1*p23A

Alder Lake-E

• Measurements
• Latencies
  • Latency operand 2 → 1: 7
  • Latency operand 3 → 1 (address, base register): ≤13
  • Latency operand 3 → 1 (address, index register): ≤13
  • Latency operand 3 → 1 (memory): ≤13
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Microcode Sequencer (MS): 0

Rocket Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p01+1*p23

Tiger Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p01+1*p23

Ice Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p01+1*p23
• Documentation
• Latency: 11.0
• Throughput: 0.5

Cascade Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.55
  • Measured (unrolled): 0.55 (if an indexed addressing mode is used: 0.54)
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p01+1*p23

Cannon Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.53
  • Measured (unrolled): 0.53
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p01+1*p23

Skylake-X

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.55
  • Measured (unrolled): 0.55
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p01+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p01+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p01+1*p23

Coffee Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.53
  • Measured (unrolled): 0.53
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p01+1*p23

Kaby Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.53
  • Measured (unrolled): 0.53
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p01+1*p23

Skylake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.53
  • Measured (unrolled): 0.53
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p01+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p01+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p01+1*p23

Broadwell

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤10
  • Latency operand 3 → 1 (address, index register): ≤10
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p01+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50 (with the -no_interiteration flag: 0.50)
• Number of μops: 2
• Port usage: 1*p01+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p01+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p01+1*p23

Haswell

• Measurements
• Latencies
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤11
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p01+1*p23
• IACA 2.1
• Latency: 12
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50 (with the -no_interiteration flag: 0.50)
• Number of μops: 2
• Port usage: 1*p01+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50 (with the -no_interiteration flag: 0.50)
• Number of μops: 2
• Port usage: 1*p01+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p01+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p01+1*p23

Ivy Bridge

• Measurements
• Latencies
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1 (address, base register): ≤13
  • Latency operand 3 → 1 (address, index register): ≤13
  • Latency operand 3 → 1 (memory): ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.02
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p0+1*p23
• IACA 2.1
• Latency: 12
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p0+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p0+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p0+1*p23

Sandy Bridge

• Measurements
• Latencies
  • Latency operand 2 → 1: 5
  • Latency operand 3 → 1 (address, base register): ≤13
  • Latency operand 3 → 1 (address, index register): ≤13
  • Latency operand 3 → 1 (memory): ≤11
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.02
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p0+1*p23
• IACA 2.1
• Latency: 12
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p0+1*p23
• IACA 2.2
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00 (with the -no_interiteration flag: 1.00)
• Number of μops: 2
• Port usage: 1*p0+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 1.00
  • IACA: 1.00
• Number of μops: 2
• Port usage: 1*p0+1*p23

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤12
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP01

AMD Zen 3

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤12
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP01

AMD Zen 2

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤11
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.50
  • Measured (unrolled): 0.50
• Number of μops
  • Executed: 1
• Port usage: 1*FP01

AMD Zen+

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤11
• Throughput
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2