VMOVNTPS (M512, ZMM)

Summary:	"Store Packed Single Precision Floating-Point Values Using Non-Temporal Hint"
Reference:	https://www.felixcloutier.com/x86/movntps
Extension:	AVX512EVEX
Category:	DATAXFER
ISA-Set:	AVX512F_512
CPL:	3
iform:	VMOVNTPS_MEMf32_ZMMf32_AVX512
iclass:	VMOVNTPS
ASM:	VMOVNTPS

Operands

Operand 1 (w): Memory
Operand 2 (r): Register (ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15, ZMM16, ZMM17, ZMM18, ZMM19, ZMM20, ZMM21, ZMM22, ZMM23, ZMM24, ZMM25, ZMM26, ZMM27, ZMM28, ZMM29, ZMM30, ZMM31)

Latencies
- Latency operand 1 → 1 (address, base register): ≤1014
- Latency operand 1 → 1 (address, index register): ≤950
- Latency operand 2 → 1: ≤1041
Throughput
- Computed from the port usage: 0.50
- Measured (loop): 21.46
- Measured (unrolled): 17.93
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p49+1*p78

Latencies
- Latency operand 1 → 1 (address, base register): ≤458
- Latency operand 1 → 1 (address, index register): ≤458
- Latency operand 2 → 1: ≤454
Throughput
- Computed from the port usage: 0.50
- Measured (loop): 6.40
- Measured (unrolled): 6.05
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p49+1*p78

Latencies
- Latency operand 1 → 1 (address, base register): ≤317
- Latency operand 1 → 1 (address, index register): ≤317
- Latency operand 2 → 1: ≤309
Throughput
- Computed from the port usage: 0.50
- Measured (loop): 5.91
- Measured (unrolled): 5.72
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p49+1*p78

Latencies
- Latency operand 1 → 1 (address, base register): ≤592
- Latency operand 1 → 1 (address, index register): ≤595
- Latency operand 2 → 1: ≤591
Throughput
- Computed from the port usage: 0.50
- Measured (loop): 6.84
- Measured (unrolled): 6.60
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p49+1*p78

Latencies
- Latency operand 1 → 1 (address, base register): ≤325
- Latency operand 1 → 1 (address, index register): ≤325
- Latency operand 2 → 1: ≤321
Throughput
- Computed from the port usage: 0.50
- Measured (loop): 5.10
- Measured (unrolled): 4.98
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p49+1*p78

Latencies
- Latency operand 1 → 1 (address, base register): ≤595
- Latency operand 1 → 1 (address, index register): ≤633
- Latency operand 2 → 1: ≤623
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 18.28
- Measured (unrolled): 17.60
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p237+1*p4 (if an indexed addressing mode is used: 1*p23+1*p4)

Latencies
- Latency operand 1 → 1 (address, base register): ≤276
- Latency operand 1 → 1 (address, index register): ≤276
- Latency operand 2 → 1: ≤279
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 6.44 (if an indexed addressing mode is used: 6.65)
- Measured (unrolled): 4.88 (if an indexed addressing mode is used: 5.04)
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p237+1*p4 (if an indexed addressing mode is used: 1*p23+1*p4)

Latencies
- Latency operand 1 → 1 (address, base register): ≤582
- Latency operand 1 → 1 (address, index register): ≤583
- Latency operand 2 → 1: ≤579
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 17.64 (if an indexed addressing mode is used: 17.63)
- Measured (unrolled): 16.98 (if an indexed addressing mode is used: 17.00)
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p237+1*p4 (if an indexed addressing mode is used: 1*p23+1*p4)