VMOVNTPS (M512, ZMM)

Summary:	"Store Packed Single-Precision Floating-Point Values Using Non-Temporal Hint"
Reference:	https://www.felixcloutier.com/x86/MOVNTPS.html
Extension:	AVX512EVEX
Category:	DATAXFER
ISA-Set:	AVX512F_512
CPL:	3
iform:	VMOVNTPS_MEMf32_ZMMf32_AVX512
iclass:	VMOVNTPS
ASM:	VMOVNTPS

Operands

Operand 1 (w): Memory
Operand 2 (r): Register (ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15, ZMM16, ZMM17, ZMM18, ZMM19, ZMM20, ZMM21, ZMM22, ZMM23, ZMM24, ZMM25, ZMM26, ZMM27, ZMM28, ZMM29, ZMM30, ZMM31)

Latencies
- Latency operand 1 → 1 (address, base register): ≤485
- Latency operand 1 → 1 (address, index register): ≤485
- Latency operand 2 → 1: ≤480
Throughput
- Computed from the port usage: 0.50
- Measured (loop): 7.87
- Measured (unrolled): 7.40
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p49+1*p78

Latencies
- Latency operand 1 → 1 (address, base register): ≤317
- Latency operand 1 → 1 (address, index register): ≤317
- Latency operand 2 → 1: ≤312
Throughput
- Computed from the port usage: 0.50
- Measured (loop): 5.90
- Measured (unrolled): 5.75
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p49+1*p78

Latencies
- Latency operand 1 → 1 (address, base register): ≤592
- Latency operand 1 → 1 (address, index register): ≤595
- Latency operand 2 → 1: ≤544
Throughput
- Computed from the port usage: 0.50
- Measured (loop): 6.75
- Measured (unrolled): 6.50
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p49+1*p78

Latencies
- Latency operand 1 → 1 (address, base register): ≤328
- Latency operand 1 → 1 (address, index register): ≤328
- Latency operand 2 → 1: ≤325
Throughput
- Computed from the port usage: 0.50
- Measured (loop): 5.11
- Measured (unrolled): 4.97
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p49+1*p78

Latencies
- Latency operand 1 → 1 (address, base register): ≤603
- Latency operand 1 → 1 (address, index register): ≤602
- Latency operand 2 → 1: ≤602
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 18.18
- Measured (unrolled): 17.57 (if an indexed addressing mode is used: 16.33)
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p237+1*p4 (if an indexed addressing mode is used: 1*p23+1*p4)

Latencies
- Latency operand 1 → 1 (address, base register): ≤270
- Latency operand 1 → 1 (address, index register): ≤276
- Latency operand 2 → 1: ≤270
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 6.86 (if an indexed addressing mode is used: 6.44)
- Measured (unrolled): 5.20 (if an indexed addressing mode is used: 4.93)
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p237+1*p4 (if an indexed addressing mode is used: 1*p23+1*p4)

Latencies
- Latency operand 1 → 1 (address, base register): ≤662
- Latency operand 1 → 1 (address, index register): ≤662
- Latency operand 2 → 1: ≤663
Throughput
- Computed from the port usage: 1.00
- Measured (loop): 17.97 (if an indexed addressing mode is used: 17.96)
- Measured (unrolled): 18.20 (if an indexed addressing mode is used: 18.36)
Number of μops
- Executed: 2
- Retire slots: 1
- Decoded (MITE): 1
- Microcode Sequencer (MS): 0
Port usage: 1*p237+1*p4 (if an indexed addressing mode is used: 1*p23+1*p4)