VADDPD (ZMM, ZMM, M512)

Operands

• Operand 1 (w): Register (ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15, ZMM16, ZMM17, ZMM18, ZMM19, ZMM20, ZMM21, ZMM22, ZMM23, ZMM24, ZMM25, ZMM26, ZMM27, ZMM28, ZMM29, ZMM30, ZMM31)
• Operand 2 (r): Register (ZMM0, ZMM1, ZMM2, ZMM3, ZMM4, ZMM5, ZMM6, ZMM7, ZMM8, ZMM9, ZMM10, ZMM11, ZMM12, ZMM13, ZMM14, ZMM15, ZMM16, ZMM17, ZMM18, ZMM19, ZMM20, ZMM21, ZMM22, ZMM23, ZMM24, ZMM25, ZMM26, ZMM27, ZMM28, ZMM29, ZMM30, ZMM31)
• Operand 3 (r): Memory

Available performance data

• Alder Lake-P
• Rocket Lake
• Tiger Lake
• Ice Lake
• Cascade Lake
• Cannon Lake
• Skylake-X
• AMD Zen 4

Alder Lake-P

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤11
  • Latency operand 3 → 1 (address, index register): ≤11
  • Latency operand 3 → 1 (memory): ≤8
• Throughput
  • Computed from the port usage: 0.50 (if an indexed addressing mode is used: 0.33)
  • Measured (loop): 0.67
  • Measured (unrolled): 0.65 (if an indexed addressing mode is used: 0.67)
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p05+1*p23A (if an indexed addressing mode is used: 1*p23A)

Rocket Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p0+1*p23

Tiger Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p0+1*p23

Ice Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p0+1*p23
• Documentation
• Latency: 11.0
• Throughput: 1.0

Cascade Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤13
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.55
  • Measured (unrolled): 0.55 (if an indexed addressing mode is used: 0.53)
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p05+1*p23

Cannon Lake

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 1.00
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p0+1*p23

Skylake-X

• Measurements
• Latencies
  • Latency operand 2 → 1: 4
  • Latency operand 3 → 1 (address, base register): ≤13
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤9
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 0.55
  • Measured (unrolled): 0.55
• Number of μops
  • Executed: 2
  • Retire slots: 1 (if an indexed addressing mode is used: 2)
  • Decoded (MITE): 1
  • Microcode Sequencer (MS): 0
• Port usage: 1*p05+1*p23
• IACA 2.3
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p05+1*p23
• IACA 3.0
• Throughput
  • Computed from the port usage: 0.50
  • IACA: 0.50
• Number of μops: 2
• Port usage: 1*p05+1*p23

AMD Zen 4

• Measurements
• Latencies
  • Latency operand 2 → 1: 3
  • Latency operand 3 → 1 (address, base register): ≤12
  • Latency operand 3 → 1 (address, index register): ≤12
  • Latency operand 3 → 1 (memory): ≤14
• Throughput
  • Computed from the port usage: 0.50
  • Measured (loop): 1.00
  • Measured (unrolled): 1.00
• Number of μops
  • Executed: 1
• Port usage: 1*FP23