Latency, Throughput, and Port Usage Information

For Instructions on Recent Intel Microarchitectures

This website provides more than 300,000 pages with detailed latency, throughput, and port usage data for most x86 instructions on all generations of Intel's Core architecture (i.e., from Nehalem to Cannon Lake). While such data is important for understanding, predicting, and optimizing the performance of software running on these microarchitectures, most of it is not documented in Intel's official processor manuals.

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XML File

A machine-readable XML file with latency, throughput, and port usage data. Contains also information on the operands of each instruction.

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Table

An interactive HTML table that makes it easy to compare different microarchitectures. Contains links to web pages with details for each entry.

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Paper

For more information, please check out our paper "uops.info Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures"

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If you have any questions, comments, or suggestions, please contact Andreas Abel at abel@cs.uni-saarland.de.